EECE 353/379 - Digital Systems Design

Instructor: Tor Aamodt

Office: KAIS 4043
Phone: 604-827-4166
Email: [email protected]

TA’s:
Tariq Al-Khasib [email protected]
Arash Takshi [email protected]

Textbook (“B&V”):
Fundamentals of Digital Logic with VHDL Design, 2nd edition,
by Stephen Brown and Zvonko Vranesic, McGraw Hill, 2004.
 Course Outline
• Boolean Alg., Combinational Logic (“Review”)
• Multiplexers, Decoders, Encoders (“Review”)
• VHDL for combinational logic
• Arithmetic Circuits: Fast adders, fast multipliers
• Flip Flops, Registers, Counters
• VHDL for sequential circuits
• State Machine Design, Minimization, Analysis

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 Course Outline Cont’d…

• ASM chart
• Detailed Design Examples: Sequential
Multiplier/Divider
• Example/Lab: Simple Microprocessor Design
• Example/Lab: Pipelined Microprocessor Design
• Transistor Level Digital Circuit Design Basics
• Asynchronous Digital Circuits

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 Big Picture

• PIP / EECE 256 : Digital Logic Design

– EECE 353 : Digital Systems Design -- You are here!
• EECE 465 : Microcomputer Systems Design
• EECE 476 : Computer Architecture
– EECE 571 : Topics in… (Advanced Computer Architecture)
• EECE 479 : Introduction to VLSI Systems
– EECE 481 : Digital Integrated Circuit Design
» EECE 579 : Advanced Topics in VLSI Design

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 Review: Boolean Algebra

• Variables and Functions

x =0 x=1
(a) Two states of a switch

S
x
(b) Symbol for a switch

B&V: Figure 2.1. A binary switch.

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 Variables and Functions cont’d…

S
Battery x Light

(a) Simple connection to a battery

B&V: Figure 2.2. A light controlled by a switch.

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 Variables and Functions cont’d…
S S
Power
supply x1 x2 Light R

(a) The logical AND function (series) Power

supply x S Light
S
x1
Power
supply S Light B&V: Figure 2.5. An inverting circuit.
x2
(b) The logical OR function (parallel)

B&V Figure 2.3. Two basic functions.

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 Variables and Functions cont’d…
• Notation

Buffer L(x) =x
AND gate L(x1,x2) = x1 • x2 = x1x2
OR gate L (x1,x2) = x1 + x2
NOT gate L(x) = x’ = !x = ~x =x

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 Variables and Functions cont’d…
• Symbols

x1
x1 x2
x2 x 1 •x2 x 1 •x2• … • xn

xn
(a) AND gates

(c) NOT gate

x1
x1 x2
x 1 +x2 x 1 +x2+ … + xn
x2
xn

(b) OR gates

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 Review: Boolean Algebra

• Truth Tables

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 Review: Boolean Algebra

Axioms Theorems (via perfect induction)

1a. 0•0 = 0 5a. x•0 = 0
1b. 1+1 = 1 5b. x+1 = 1
2a. 1•1 = 1 6a. x•1 = x
2b. 0+0 = 0 6b. x+0 = x
7a. x•x = x
3a. 0•1 = 1•0 = 0
7b. x+x = x
3b. 1+0 = 0+1 = 1
8a. x •x’ =0
4a. If x=0, then x’ = 1 8b. x+x’ = 1
4b. If x=1, then x’ = 0 9. x’’ = x

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 Review: Boolean Algebra
Two- and Three- Variable Properties
Commutative Combining
10a. x•y = y•x 14a. x•y + x•y’ = x
10b. x+y = y+x
14b. (x+y)•(x+y’) = x
Associative DeMorgan’s theorem
11a. x•(y•z) = (x•y) •z 15a. (x•y)’ = x’ + y’
11b. x+(y+z) = (x+y)+z 15b. (x+y)’ = x’ • y’
Distributive
12a. x•(y+z) = x•y + x•z 16a. x+x’•y = x+y
12b. x+y•z = (x+y)•(x+z) 16b. x•(x’+y) = x•y
Absoption
Consensus
13a. x+x•y = x
17a. x•y+y•z+x’•z = x•y + x’•z
13b. x•(x+y) = x
17b. (x+y)•(y+z)•(x’+z) = (x+y)•(x’+z)

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 Review: Boolean Algebra
Proof techniques
(a) Truth Table (b) Venn Diagram

(a) Constant 1 (b) Constant 0

x x
x’ (c) Variable x x’ (d) x’

x y (e) x•y
x y (f) x+y

x y (h) z+x•y
x y (g) x•y’
B&V: Figure 2.11. Proof of z
DeMorgan’s theorem in 15a.

B&V: Figure 2.12. The Venn diagram representation.

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 Venn Diagram Proof Example
x y x y

z z

x•y x•y


x y x y

z z

x’•z x’•z

x y x y

z z

y•z x•y + x’•z

x y

x•y + y•z + x’•z

B&V: Figure 2.14. Verification of x•y + y•z + x’•z = x•y + x’•z

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Review: Combinational vs. Sequential Logic

Combinational
N inputs … … M outputs Outputs depend ONLY upon inputs
circuit

General Form of a combination logic circuit

W Combinational Combinational
Flip-flops circuit Z
circuit Q

Clock

B&V: Figure 8.1. The general form of a sequential circuit.

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 Review: 2-Level Combinational Logic
Synthesis and Optimization

Example Problem Desired: low cost solution

x1
x2

(a) Canonical sum-of-products

B&V: Figure 2.15. A function
to be synthesized. x1
x2 f

(b) Minimal-cost realization

B&V: Figure 2.16. Two implementations

of a function in Figure 2.15.

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Review: 2-Level Combinational Logic Synthesis and Optimization

Sum-of-Products/Product-of-Sums

B&V: Figure 2.17 Three-variable minterms and maxterms.

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 Review: 2-Level Combinational Logic Synthesis and Optimization

Example

f(x1,x2,x3) = ∑m(1,4,5,6)
=> f’(x1,x2,x3)= ∑m(0,2,3,7)
=> f = (m0+m2+m3+m7)’
=> f = m0’•m2’•m3’•m7’
=> f = M0•M2•M3•M7

B&V: Figure 2.18. A three-

variable function.

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Review: 2-Level Combinational Logic Synthesis and Optimization

Example cont’d…
x2

x3 f
x1
(a) A minimal sum-of-products realization

x1
x3
f
x2

(b) A minimal product-of-sums realization

B&V: Figure 2.19. Two realizations of a function in Figure 2.18.

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 Aside: NAND and NOR realizations

x1 x1 x1 x1
x2 x2 x2 x2
x3 x3 x3 x3
x4 x4 x4 x4
x5 x5 x5 x5

x1 x1
x2 x2
x3 x3
x4 x4
x5 x5

B&V: Figure 2.22. Using NAND gates to B&V: Figure 2.23. Using NOR gates to
implement a sum-of-products. implement a product-of sums.

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 Review: 2-Level Combinational Logic Synthesis and Optimization
Karnaugh Maps
recall properties 14a&b (combining) on slide 12
x1 x2 x1 x2
x3x4 x3x4
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0

01 0 0 1 1 01 0 0 1 1

11 1 0 0 1 11 1 1 1 1

10 1 0 0 1 10 1 1 1 1

f 1 = x2x3 + x1x3x4 f2 = x3 + x1 x
4

x1 x2 x1 x2
x3x4 x3x4
00 01 11 10 00 01 11 10
00 1 0 0 1 00 1 1 1 0

01 0 0 0 0 01 1 1 1 0

11 1 1 1 0 11 0 0 1 1

10 1 1 0 1 10 0 0 1 1

x1 x2
f 3 = x2x4 + x1 x3 + x2x3x4 f4 = x1 x3 + x1 x3 + or
x2x 3

B&V: Figure 4.7. Examples of four-variable Karnaugh maps.

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 Introduction to VHDL
Design conception
Step 1: Describe System (e.g.
DESIGN ENTRY “flow chart”, “requirements”)
Schematic
VHDL
capture
Step 2: Think about the hardware
Synthesis
you want to build! Building blocks.

Functional simulation
Step 3: Only then, write VHDL
No
Design correct?
Yes
Hardware Description Languages
Physical design
CHALLENGE: If you do step 3
Timing simulation without or before the other two,
No you are (very likely) going to end up
Timing requirements met? with a poor quality circuit. This
Chip configuration
isn’t a programming course!

B&V: Figure 2.29. A typical CAD system.

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 Trends in HW Design
(i.e. - “why you should NOT write your VHDL
as if you were writing a program”)

• “In the beginning…” Full custom design - draw

polygons. Still done today for circuits required to
achieve high frequency operation.
• Now: RTL (register transfer level) design…
standard cell, FPGA, etc… You should be able
to predict what the hardware will look like!
• High Level Synthesis… Goal: take your “C”
program and generate a chip. Less insight into
what the design tools have generated (if they
generate anything at all).

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VHDL: Basic Language Organization
(courtesy of H. Alnuweiri - EECE Spring 2006 353/379 slides)

• Basic construct for modeling a digital system in VHDL is

called a design entity.
• A VHDL design entity consists of two parts
– An interface denoted by the keyword “entity”
The interface describes aspects of the digital system visible to the
outside world.
– A body denoted by the keyword “architecture”
The body describes aspects of the digital system that defines how the
outputs respond to the input (or input changes)
• Division of design entity into an interface and body implies
the separation of specification from implementation

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 “Hello World” Example*
x1
x2
f
ENTITY example1 is
x3
PORT( x1, x2, x3 : IN BIT ;
B&V: Figure 2.30. A simple f : OUT BIT );
logic function. END example1;

ARCHITECTURE LogicFunc OF example1 IS

BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3);
END LogicFunc

*this VHDL does not print “hello world”… most programming books traditionally begin with an
example that shows how to print “hello world”. VHDL is for designing hardware, so to emphasize
that point (again), this example does NOT print out anything since it just describes a handful of
gates.

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 Suggested Reading

• Brown and Vranesic

– Chapter 2, Sections 5, 6, 7, 8, 9, and 10.
– Chapter 4, Sections 1, 2, 4, 5, 6, 8, 9, and 10.
– Chapter 6, Sections 1, 2, 3, 4, 6.

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