Lec4.

4
POWER DESIPATION
Engr. Anees ul Husnain ( [email protected] )

Department of Computer Systems Engineering,

College of Engineering & Technology, IUB
Power and Energy

 Power is drawn from a voltage source attached to the VDD

pin(s) of a chip.

 Instantaneous Power: P (t )  iDD (t )VDD

T T

 Energy: E   P(t )dt   iDD (t )VDD dt

0 0
T
E 1
 Average Power: Pavg    iDD (t )VDD dt
T T 0
Power Dissipation

 Static Power Dissipation

 Sub-thresh hold conduction
 Tunneling Current
 Leakage through diode

 Dynamic Power Dissipation

 Charging & Discharging of load Capacitances
 Short circuit currents while both N-MOS & P-MOS are ON together.

P total =P static +P dynamic

Dynamic power

 Dynamic power is required to charge and discharge load

capacitances when transistors switch.

 One cycle involves a rising and falling output.

 On rising output, charge Q = CVDD is required

 On falling output, charge is dumped to GND VDD

iDD(t)
 This repeats Tfsw times over an interval of T

C
fsw
 Dynamic power dissipation
Vdd

load capacitance (gate +

Vin Vout
diffusion + interconnects)

CL

Energy delivered by the supply during input 1  0

transition:

Energy stored at the capacitor at the end of 1  0 transition:

dissipated in NMOS during

discharge
(input: 0  1)
Capacitive dynamic power

 If the gate is switched on and off f01 (switching factor) times per second,
the power consumption is given by

 For entire circuit

where αi is activity factor [0..0.5] in comparison to the clock frequency

(which has switching factor of 1)

Pdynamic   CVDD f 2
Short circuit current

 When transistors switch, both nMOS and pMOS networks may be momentarily
ON at once

 Leads to a blip of “short circuit” current.

 < 10% of dynamic power if rise/fall times are comparable for input and output
Techniques for low-power design Pdynamic   CVDD 2 f

 Reduce dynamic power

 : clock gating, sleep mode (floating point, caches,etc)

 Fast transitions.. (may become noisy.. Tradeoff)

 C: small transistors (esp. on clock), short wires (bus length )

 VDD: lowest suitable voltage

 f: lowest suitable frequency

Clock Gating
 The best way to reduce the activity is to turn off the clock to registers in
unused blocks
 Saves clock activity ( = 1)
 Eliminates all switching activity in the block
 Requires determining if block will be used

Clock

Enable

Clock Gating
Dynamic power reduction via dynamic VDD scaling

 Scaling down supply voltage Pdynamic   CVDD 2 f

 reduces dynamic power
 reduces saturation current
 increases delay  reduce the frequency

Dynamic voltage scaling (DVS):

Supply and voltage of the circuit should dynamic adjust according to the
workload of criticality of the tasks running on the circuits

e.g: laptops in case connected with ac and on batteries.

Leakage reduction via adjusting of Vth

 Leakage depends exponentially on Vth. How to control Vth?

 Remember: Vth also controls your saturation current  delay

1. Oxide thickness

Sol1: statically choose high Vt cells for

non critical gates

I1
I2 O1
I3
I4
I5 O2
I critical
6 path
Static (leakage) power

 Static power is consumed even when chip is quiescent.

 Leakage draws power from nominally OFF devices

Vgs Vt
 Vds

I ds  I ds 0e nvT
1  e 
vT

 
Leakage Control
 Leakage and delay trade off
 Aim for low leakage in sleep and low delay in active mode

 To reduce leakage:

 Increase Vt: multiple Vt

 Use low Vt only in critical circuits

 Increase Vs: stack effect (series OFF transistors have less leakage)
 Input vector control in sleep

 Decrease Vb
 Reverse body bias in sleep
 Or forward body bias in active mode
Gate Leakage

 Extremely strong function of tox and Vgs

 Negligible for older processes
 Approaches subthreshold leakage at 65 nm and below in some processes

 An order of magnitude less for pMOS than nMOS

 Control leakage in the process using tox > 10.5 Å

 High-k gate dielectrics help
 Some processes provide multiple tox
 e.g. thicker oxide for 3.3 V I/O transistors

 Control leakage in circuits by limiting VDD

Power Gating
 Turn OFF power to blocks when they are idle to save leakage
 Use virtual VDD (VDDV)
 Gate outputs to prevent
invalid logic levels to next block

 Voltage drop across sleep transistor degrades performance during

normal operation
 Size the transistor wide enough to minimize impact

 Switching wide sleep transistor costs dynamic power

 Only justified when circuit sleeps long enough
Leakage reduction via Cooling

 Impact of temperature on leakage current

Summary
We are still in chapter 4:
 Delay estimation
 Power estimation
 Interconnects and wire engineering
 Scaling theory