0% found this document useful (0 votes)

31 views20 pages

Lesson 9.1 - Sequential Logics - Latch

Uploaded by

omar fawzy

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

31 views20 pages

Lesson 9.1 - Sequential Logics - Latch

Uploaded by

omar fawzy

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

You are on page 1/ 20

DIGITAL LOGICS

(SMJE 1113)
LESSON 9.1

LATCH
Introduction to sequential logics
• The logic circuits considered thus far have been combinational logic circuits whose
output levels at any instant of time are dependent on the levels present at the
inputs at that time. Any prior input-level conditions have no effect on the present
outputs because combinational logic circuits have no memory.
• There is another kind of logic circuit where the outputs of a digital system are
functions of both its inputs and its previous output that has been stored in its
memory elements. - Sequential logics

Sequential Logics

3
Introduction to sequential logics
• The most important memory element is the flip-flop, which is made up
of an assembly of logic gates.
• Even though a logic gate, by itself, has no storage capability, several can be
connected together in ways that permit information to be stored. Several
different gate arrangements are used to produce these flip-flops
(abbreviated FF).

4
General flip-flop symbol Definition of its two possible output states.
Latch
The most basic FF circuit can be constructed from either two NAND gates or
two NOR gates. The NAND gate version, is called a NAND gate latch or
simply a latch
0

One possibility when SET=1, RESET=1 Another possibility when SET=1, RESET=1
If momentarily previous output of Q = 0 If momentarily previous output of Q = 1
5
Latch
A latch is bi-stable device i.e. it has 2 stable states – at logic HIGH and LOW

Active LOW S-R Latch Active HIGH S-R Latch

Latch
A latch is bi-stable device i.e. it has 2 stable states – at logic HIGH and LOW

Active HIGH S-R Latch

Active LOW S-R Latch
05/31/2021 8
05/31/2021 9
S R Q
0 0 No change
0 1 Reset , Q=0
1 0 Set, Q=1
1 1 Invalid
condition
05/31/2021 10
Example 1:

set nc set nc set nc

nc reset reset nc reset nc
nc

05/31/2021 11
Example 2:

SET

RESET

set
set

reset
reset

05/31/2021 12
Example 2:

set nc set nc
Re-
Re-
nc set nc nc
set
set

reset
reset

05/31/2021 13
14
Application of
S’-R’ Latch:

05/31/2021 15
0
1=set
1 S’
set
X

0 1 No change

Y
1 R’ reset
0
1=reset S’ – R’ Latch

If EN= 1, X= S’, Y=R’, the S’R’ latch behaves as it should

If EN=0. X= 1, Y= 1, the S’R’ latch will be NC

16
Re- set set
set nc
set
nc reset

If EN= 1, X= S’, Y=R’, the S’R’ latch behaves as it should

If EN=0. X= 1, Y= 1, the S’R’ latch will be NC

17
Gated S-R latch
S=0 R= 0 Q = NC
S’-R’ latch S=D=0 R=1 Q=0 Reset
S
S’ S=D=1 R=0 Q=1 set
S=1 R=1 Q=invalid

D Q
0 0 reset
SR 1 1 set

Truth table of
Gated D-Latch

Gated-D latch
R’ eliminates the
R problem of
uncertainty when
input S=R = 0/1

Gated D latch Infact, D-latch is one of the

most widely used latch until
today 18
19
Exercise –

Observe the timing diagram of the Gated-D Latch shown.