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    Parameters of Cache Memory: - Cache Hit - Cache Miss - Hit Ratio - Miss Penalty

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    Majety S Lskshmi
    This document summarizes key parameters and concepts related to cache memory. It discusses cache hits, misses, hit ratio, and miss penalty. It also covers cache latency, bandwidth, block replacement policies like LRU and FIFO, write-through and write-back update policies, sources of cache misses, cache organization approaches like split vs unified caches, and multilevel cache hierarchies with L1 and L2 caches. Performance is analyzed using concepts like look-through vs look-aside caching and calculating average memory access times.

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    Parameters of Cache Memory: - Cache Hit - Cache Miss - Hit Ratio - Miss Penalty

    Uploaded by

    Majety S Lskshmi
    161 views18 pages
    This document summarizes key parameters and concepts related to cache memory. It discusses cache hits, misses, hit ratio, and miss penalty. It also covers cache latency, bandwidth, block replacement policies like LRU and FIFO, write-through and write-back update policies, sources of cache misses, cache organization approaches like split vs unified caches, and multilevel cache hierarchies with L1 and L2 caches. Performance is analyzed using concepts like look-through vs look-aside caching and calculating average memory access times.

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    FALLSEM2020-21_CSE2001_TH_VL2020210104493_Reference_Material_I_31-Aug-2020_PROBLEMS_-_CACHE_MEMORY

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    This document summarizes key parameters and concepts related to cache memory. It discusses cache hits, misses, hit ratio, and miss penalty. It also covers cache latency, bandwidth, block replacement policies like LRU and FIFO, write-through and write-back update policies, sources of cache misses, cache organization approaches like split vs unified caches, and multilevel cache hierarchies with L1 and L2 caches. Performance is analyzed using concepts like look-through vs look-aside caching and calculating average memory access times.

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    Download as pptx, pdf, or txt
    161 views18 pages

    Parameters of Cache Memory: - Cache Hit - Cache Miss - Hit Ratio - Miss Penalty

    Uploaded by

    Majety S Lskshmi
    This document summarizes key parameters and concepts related to cache memory. It discusses cache hits, misses, hit ratio, and miss penalty. It also covers cache latency, bandwidth, block replacement policies like LRU and FIFO, write-through and write-back update policies, sources of cache misses, cache organization approaches like split vs unified caches, and multilevel cache hierarchies with L1 and L2 caches. Performance is analyzed using concepts like look-through vs look-aside caching and calculating average memory access times.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    of 18

    Parameters of Cache memory

    • Cache Hit
    • A referenced item is found in the cache by the processor
    • Cache Miss
    • A referenced item is not present in the cache
    • Hit ratio
    • Ratio of number of hits to total number of references => number of
    hits/(number of hits + number of Miss)
    • Miss penalty
    • Additional cycles required to serve the miss
    Parameters of Cache Memory
    • Time required for the cache miss depends on both the latency and
    bandwidth
    • Latency – time to retrieve the first word of the block
    • Bandwidth – time to retrieve the rest of this block
    Problems
    • A set associative cache consists of 64 lines or slots, divided into four
    line sets. Main memory consists 4Kblocks of 128 words each. Show
    the format of main memory addresses.
    Problem 2
    • A two-way set associative cache has lines of 16 bytes and a total size
    of 8k bytes. The 64-Mbyte main memory is byte addressable. Show
    the format of main memory addresses.
    Block Replacement
    • Least Recently Used: (LRU)
    Replace that block in the set that has been in the cache longest
    with no reference to it.
    • First Come First Out: (FIFO)
    Replace that block in the set that has been in the cache longest.
    • Least Frequently Used: (LFU)
    Replace that block in the set that has experienced the fewest
    references
    Update Policies - Write Through
    • Update main memory with every memory write operation
    • Cache memory is updated in parallel if it contains the word at
    specified address.
    • Advantage: main memory always contains the same data as the cache
    • It is important during DMA transfers to ensure the data in main
    memory is valid
    • Disadvantage: slow due to memory access time
    Write Back
    • Only cache is updated during write operation and marked by flag.
    When the word is removed from the cache, it is copied into main
    memory
    • Memory is not up-to-date, i.e., the same item in cache and memory
    may have different value
    Update policies
    • Write-Around
    • correspond to items not currently in the cache (i.e. write
    misses) the item could be updated in main memory only
    without affecting the cache.
    • Write-Allocate
    • update the item in main memory and bring the block
    containing the updated item into the cache.
    Performance analysis
    • Look through: The cache is checked first for a hit, and if a miss occurs
    then the access to main memory is started.
    • Look aside: access to main memory in parallel with the cache lookup;
    •Look through
    TA = TC + (1-h)*TM
    TC is the average cache access time
    TM is the average access time
    (Mean memory access time)

    •Look aside
    TA = h*TC + (1-h)*TM

    number of references found in the cache


    •hit ratio h =
    total number of memory references

    • Miss Ratio m=(1-h)


    Example: assume that a computer system employs a cache with an access time of 20ns and a main memory with
    a cycle time of 200ns. Suppose that the hit ratio for reads is 90%,

    a) what would be the average access time for reads if


    the cache is a “look-through” cache?

    The average read access time (TA) = TC + (1-h)*TM


    20ns + 0.10*200ns = 40ns

    b) what would be the average access time for reads if


    the cache is a “look-Aside” cache?
    The average read access time in this case (TA)
    = h*TC + (1-h)*TM= 0.9*20ns + 0.10*200ns = 38ns
    Problem
    • Consider a memory system with Tc = 100ns and Tm =
    1200ns. If the effective access time is 10% greater
    than the cache access time, what is the hit ratio H in
    look-through cache?
    Þ TA = TC + (1-h)*TM
    Þ 1.1 Tc = Tc + (1-h)*TM
    Þ 0.1TC = (1-h)* TM
    Þ0.1 * 100 = (1-h) *1200
    Þ1-h = 10/1200
    Þh = 1190/1200
    Sources of cache Misses
    • Compulsory Misses
    • Capacity Misses
    • Cold Misses
    • Conflict Misses
    Sources of Cache Misses
    • Compulsory Misses: These are misses that are caused by the
    cache being empty initially.
    • Cold Misses : The very first access to a block will result in a miss
    because the block is not brought into cache until it is referenced.
    • Capacity Misses : If the cache cannot contain all the blocks
    needed during the execution of a program, capacity misses will
    occur due to blocks being discarded and later retrieved.
    • Conflict Misses: If the cache mapping is such that multiple blocks
    are mapped to the same cache entry
    Cache organization
    • Split cache
    • Separate caches for instructions and data
    • I-cache (Instruction) – mostly accessed sequentially
    • D-cache (data) – mostly random access
    • Unified cache
    • Same cache for instruction and data
    • Higher hit rate for unified cache as it balances
    between instruction and data
    • Split caches eliminate contention for cache between
    the instruction processor and the execution unit –
    used for pipelining processes
    Multilevel caches
    • The penalty for a cache miss is the extra time that it takes to
    obtain the requested item from central memory.
    • One way in which this penalty can be reduced is to provide
    another cache, the secondary cache, which is accessed in
    response to a miss in the primary cache.
    • The primary cache is referred to as the L1 (level 1) cache and
    the secondary cache is called the L2 (level 2) cache.
    • Most high-performance microprocessors include an L2 cache
    which is often located off-chip, whereas the L1 cache is located
    on the same chip as the CPU.
    • With a two-level cache, central memory has to be accessed
    only if a miss occurs in both caches.
    Example:
    • A computer system employs a write-back cache with a 70% hit
    ratio for writes. The cache operates in look-aside mode and has
    a 90% read hit ratio. Reads account for 80% of all memory
    references and writes account for 20%. If the main memory
    cycle time is 200ns and the cache access time is 20ns, what
    would be the average access time for all references (reads as
    well as writes)?
    The average access time for reads = 0.9*20ns + 0.1*200ns =
    38ns.
    The average write time = 0.7*20ns + 0.3*200ns = 74ns
    Hence the overall average access time for combined reads and
    writes is
    0.8*38ns + 0.2*74ns = 45.2ns
    References
    • J. L. Hennessy & D.A. Patterson, Computer architecture: A quantitative
    approach, Fourth Edition, Morgan Kaufman, 2004.

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