Analog and Digital

x x

t t

• An analog signal is continuous • A digital signal is measured at

along both axes. Continuous in discrete time instants and can
time. Continuous values. attain discrete set of values.
 ADC & DAC
• Transducers convert physical/ real world signals to an electrical equivalent. These
are mostly analog signals.
• Signals within the microcomputer are digital signals. The microcomputer
understands only the binary data format. A binary signal is also a digital signal.
• Interfacing the microcomputer to the physical world requires inter-conversion
between analog and digital formats.
• Sampling then quantization are the steps involved in analog to digital conversion.
• A digital signal is only an approximate replica of an analog signal. An analog signal
contains infinite information, while a digital signal retains only essential
information.
• Encoding is a further step required to convert to binary format.
• Interpolation or other techniques are used to revert a digital signal back to analog.
• ADC (Analog to Digital Converter) are integrated chips used to convert an analog
signal to digital.
• Similarly, DAC (Digital to Analog Converter) are used to convert digital signals to
analog.
 Sampling x

fs
t
TTransducer x

t Sampling

• Sampling means to take measurements at regular intervals.

• A sampled signal is a discrete signal, not yet a digital signal.
• Sampling rate (fs) is the no. of samples taken per second.
• Sampling discards information in between samples.
• Sampled signal is an approximation of analog signal.
• Higher the sampling rate, closer is the approximation.
• What is the minimum rate at which sampling can be performed,
still maintaining a good approximation?
 Nyquist rate
• Minimum sampling rate such that the original signal can be
reconstructed.
• Nyquist rate= 2 x Signal Bandwidth (max freq: f0)
• Undersampling is sampling at lesser than the Nyquist rate.
• Undersampling causes aliasing. Reconstructed signal has
different freq than original, nowhere similar to the original.
Undersampling is not recommended.
• Oversampling increases redundancy but reconstructed signal
is more accurate.
• Oversampling ratio: OSR=fs/2f0

• SNR (Signal to Noise Ratio) improves with oversampling

 Quantization
• Range of Input values [0, Vref] divided into M discrete levels.
• Quantization Step(∆) = Difference between two consecutive
levels.
• Every sample value rounded to nearest level.
• Quantization error: actual value- rounded value.
• Quantization error is a random variable in the range
[-∆/2, + ∆/2]. Error signal is quantization noise signal.
rms value:

• Oversampling is necessary to compensate for quantization

noise. Quantization noise power:
x

Quantization error
Quantization
Step

t
 Encoding
• M=2n voltage levels can be encoded into binary with
‘n’ bits. Every quantized sample encoded.
• Microprocessor data: sequence of bits (n bits for
one sample)

• Resolution

• SNR improves with more no. of bits for every

sample.
 x

1100
1011
1010
1001
1000
0111 t
0110
0101
0100
0011
0010
0001
0111 1011 1010 0110 0010 0010 0110 1010 1010 0111 0100 0010 0011 0110
0000
 DAC Parameters
• Resolution of a DAC is determined by the number of bits in the input word. For example, the
resolution of an 8-bit DAC is expressed as 1 part in 28 or 256, OR, sometimes expressed in
percentage as
(1/256) x 100=0.39%.
• Full scale o/p voltage is the maximum possible o/p when all input bits are 1. For example, an 8-
bit, 10V DAC will produce (1/256)x10Vx(1111)2=9.961V
However, the DAC must always be referred to as 10V DAC.
• Accuracy of a DAC is the deviation of the actual o/p voltages from the expected and is
expressed in percentage. For example, an 8-bit, 10V DAC with ±0.2% accuracy will have a
maximum error of 0.002x10V=20mV and may produce o/p in the range 9.941 to 9.981 for the
input 1111.
• Linearity is a desired characteristics of an ideal DAC, which means that the i/p to o/p
relationship must be on a straight line. For example, a linear 8-bit, 10V DAC will produce o/p
voltages of 0, 0.039, 0.078, 0.117,…. for inputs 0000, 0001, 0010, ….
• Settling time is the duration required for transition to a new o/p voltage. During transition, the
o/p usually overshoots then oscillates, gradually decaying, before settling on the new value.
• Monotonicity means always increasing or always decreasing o/p characteristics for increasing
i/p. In case of DAC, it is always increasing, unless otherwise designed.
• Temperature Coefficient determines the dependence of accuracy of a DAC on ambient
temperature.
 Binary Weighted Resistor Network(WRN) DAC

• Single Pole Double Through (SPDT) switches controlled by N-bit input digital word (bN-1….b1b0)2.

• The values of the resistors is

distributed over a wide range and
is hence, IC fabrication is
impractical for larger word sizes.
• Highly dependant upon the
precision of resistors and
temperature.
• High power consumption.
• Current type DAC.
 R-2R Ladder Network DAC

• SPDT switches controlled by N-bit input digital word (bN-1….b1b0)2.

• IC fabrication relatively easier, since, only R or 2R resistors are used.
• V0=VRef/D
• Examples are Motorola MC1408 8-bit DAC, National Semiconductor
10-bit DAC1020,DAC1021, DAC1022, 12-bit DAC1208, DAC1230,….
 ADC Parameters
• Resolution:
The resolution (quantization step) of an ADC is the smallest
change that can be distinguished in the analog input.
Resolution = FSR (Full Scale Range) / 2n
• Conversion Time
The total time required to convert an analog signal into
digital output. This dictates the maximum frequency analog
signal that can be converted to digital with good accuracy.
• Linearity and Accuracy
 Successive Approximation ADC

• Initially, SAR outputs a 1 in the MSB position.

• The corresponding analog equivalent Vo is compared with the analog input Vin.
If Vin-Vo is greater, the 1 is retained, else, complemented.
• The same algorithm is applied for the next bit position, until, the LSB position.
• The Successive approximation ADC is a popular ADC with a fixed conversion
time. E.g: National Semiconductors ADC1208, ADC0816,….
 Counter based/ Ramp type ADC

• Counter keeps counting with every clock pulse until its analog
equivalent exceeds the analog input voltage.
• This count is the digital output.
• Conversion time directly proportional to the analog input
voltage.
 Parallel Comparator/ Flash type ADC

• Vref is divided as per

quantization levels by a
series of resistors.
• Analog input is compared
with each level and a
priority encoder encodes
into digital, the highest
level lower than Vin.

• Most complex since M=2n comparators are required.

• Fastest (used even for video signal), the delay is just equal to gate delay.
• Parallel comparators are interfaced in DMA mode, because, the
microprocessor is unlikely to be reading data as fast as the ADC would be
producing data.
 Dual Slope ADC
• A ramp generator/ integrator is the main
functional block in the Dual Slope ADC.
• Negative –VREF is required for positive voltages
and vice versa.
• Initially, all counters and capacitor are reset.
Switch switches to Vin and capacitor starts
charging by I=- Vin /RC with a negative slope
directly proportional to input voltage. Due to
negative capacitor voltage, comparator
throughs the CLK and the counter starts
counting. This phase exists for a fixed count/
time after which the counter is reset.
• Next, –VREF discharges the capacitor with
current: I= VREF /RC, a positive and constant
slope. When the capacitor voltage discharges
to zero, the CLK is diabled and counting stops.
The time/ count is directly proportional to the
input voltage.
• Examples are Intersil ICL7136, ICL7135,
ICL8068, ICL7104-16.
• Slow conversion time.
• Data is output in a multiplexed BCD or 7-
segment form. Hence, is used mostly in digital
voltmeters, etc.
 Polled ADC Interfacing

• Here ADC digital outputs are connected to the data bus of the microprocessor.
• We need one output port to send a START pulse and two input ports one to
check the status of DR line and the other to read the output of the converter.
Interrupt based ADC Interfacing
• The ADC0801 is designed to be
microprocessor compatible. It
has four control signals for
interfacing : CS , WR, RD and
INTR.
• To start conversion, the
microprocessor has to OUT to
port, CS and WR signals are
asserted low.
• The ADC0801 has necessary
logic built-in-chip to generate an
INTR after conversion
completes. The microprocessor
simply has to read from port,
when an interrupt is received.
• The INTR line is then reset.
• The ADC0801 can be connected
to behave as a memory location
or an I/O device.
 Service Routine when used as an I/O device

IN 80h ;Read ADC

; assumed at 80h
MOV M,A ; Save in memory
INX H ; Next memory location
OUT 80h ; Initiate next cycle
EI ; Wait for interrupt
RET

Service Routine when used as a memory location

LDA 8000h ; Read ADC

; assumed at 8000h
MOV M,A ; Save in memory
INX H ; Next memory location
STA 8000h ; Write to ADC to ; Initiate next
cycle
EI ; Wait for interrupt
RET
 8255 based ADC Interfacing
• Alternatively, an 8255 could be
used instead of directly connecting
to the microprocessor.
• The digital o/p(s) of the ADC can
be connected to port A, configured
in Mode 1, strobed input. The DR
line can be connected to STB input
on the ADC.
• START signal can be provided from
one of the remaining pins of Port
C, configured as output pins, using
BSR mode.
• Interrupt can be disabled to used
Polled mode or enabled to be used
as Interrupt based.