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EE-307 Fpga Based System Design: Lecture # 03

The document discusses a lecture on combinational logic in Verilog. It covers modules in Verilog, instantiating modules, and gate-level modeling. It provides examples of half adder and full adder modules in Verilog, including instantiating a half adder module within a full adder module. The document also discusses data types in Verilog like nets, regs, vectors, memories and others.

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Muhammad Anas
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77 views19 pages

EE-307 Fpga Based System Design: Lecture # 03

The document discusses a lecture on combinational logic in Verilog. It covers modules in Verilog, instantiating modules, and gate-level modeling. It provides examples of half adder and full adder modules in Verilog, including instantiating a half adder module within a full adder module. The document also discusses data types in Verilog like nets, regs, vectors, memories and others.

Uploaded by

Muhammad Anas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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EE-307

FPGA BASED SYSTEM DESIGN


Spring 2015

Verilog
Combinational Logic in Verilog

Lecture # 03
2 Verilog Basics
Today’s Lecture

 Modules in Verilog
 Instantiating a Module
 Gate Level Modeling in Verilog
Verilog
4

 HW or SW ?
 Verilog --- Programming language ?
 Verilog
 HW Description
 In H/W Everything is always active
 Creates your Datapath/Circuit
 Its simulation is Event Based
 The synthesis tool understands only a subset of
Verilog, the part of Verilog called ‘RTL Verilog’
Is Verilog Simulation event based
?

Is the synthesized H/W also


event based ?
Verilog
Data Types
6
 net
 Connection between hardware elements
 Default value Z  High Impedance [not driven by circuit, the signal is neither driven to a logical high
nor low level ]
 Declared as Wire
 reg
 Can act as A variable that holds a value … (need to be careful)?
 Synthesizable to register or latch
 Declared as reg
 Initial state is Unknown (X) in Verilog Simulation
 Vectors Word Size
 wire [7:0] data_bus; // A bus of width 8
 //8 bit bus, with bit-7 as the most significant
 Memories
 reg mem1bit [0:1023]; // 1K 1 bit words
 reg [7:0] membyte [0: 1023]; // 1K 8 bit words

 Others
 Integer, Real, Time, Arrays, Strings, Parameters
Examples
 wire [low# : high#] or wire [high# : low#]
 The first # defines the MSB
 Example
 Wire [2:0] a = 3’b001; // Bit 2 is the MSB  (Use This)
 Wire [0:2] a = 3’b001; // Bit 0 is the MSB
 Assigning value to a part-select of vector
 wire [31:0] a,b,c;
 a[31] = 1’b1
 //Above means we are making the MSB of a equal to 1
 You can’t change the order of MSB after declaration

Leave : Variable Vector Part Select


Verilog 2001 allows
Multi-Dimensional Arrays
8

 Xilinx allows upto 3D arrays (Correct for 2011 )


 Declaring 3D array
 //////////////// 3 D Array
 reg [7:0] d [0:3][0:1][0:1];
 Accessing 3D Array
 d[1][0][0] = data; // = 8’b01010111;
 d[1][0][0] [3:0]= 4’b1010;
 Accessing parts of an element of 3D Array
 e = d[3][1][0][3:0];
 http://www.sutherland-hdl.com/papers/2000-HDLCo
n-paper_Verilog-2000.pdf
Constants
Verilog
10

 Comments //
 Number Specification
 2’b11 // 2 bit binary number
 Without base formatdecimal numbers e.g. 11 is a decimal no.
 Without size  simulator/machine specific, e.g: ‘h11 is a 32 bit no.
 12’hCDF // 12 bit hex number
 -3’d1 // 3 bit 2’s complement of 1
 Keywords & Identifiers
 wire Write_enable; // wire is a keyword & Write_enable is an identifier
 Logic Values: 0,1 & ..X,Z
 Unknown Value: X, e.g. Un-initialized value, A net driven by two primitives
 High Impedance:
It is important Z, e.g. Tristate
to remember Buffer,
that there is noBi-directional I/O
X (unknown value) in a real circuit [SHO]
What shall be the value of
a, b and c

wire [3:0]a = 4’d11;


wire [3:0]b = 4’b0011;
wire [3:0]c = 4’b11;
Verilog -- Design Levels
12

 Gate-Level modelling
 Verilog gate Primitives
 Dataflow Modelling
 Continuous Assignment using assign statement
 Expressions, Operators, Operands
 Behavioural Modelling
 Structured Procedures: Initial & always blocks
 Blocking & Non-blocking statements
 HLL Higher language constructs (if, switch, case, loops)
Verilog Module

 Consider a very simple design


 We want to make a Full Adder

HA

HA

FA
Verilog HALF Adder & FULL Adder
module HA_GateLevel(
input a, b ,
output c_out, sum
);

xor x1 (sum,a,b);
and and1 (c_out,a,b);

endmodule

gate_name instance_name(out,in1,in2)

[CIL]
Basic Verilog Module
Verilog 2001 Verilog 1995
Module Declaration & module HA_GateLevel( module HA_GateLevel (a,b,c_o,s_o);
Port Listing
input a, b , input a,b;
output c_o, s_o output c_o, s_o;
Intermediate );
Connections, Wire
Declarations

Module Logic xor (s_o,a,b); xor (s_o,a,b);


Comb./Seq. and (c_o,a,b); and (c_o,a,b);

End Module endmodule endmodule


module FA(
Module
input a,b,c_in,
Declaration &
output sum, cout
Port Listing
);
Intermediate
Connections, Wire wire s1,c1,c2;
Declarations
HA_GateLevel HAB1 ( module HA_GateLevel(
.a(a), input a, b ,
output c_o, s_o
.b(b), );
Instantiation
.c_o(c1), xor (s_o,a,b);
of and (c_o,a,b);
.s_o(s1) endmodule
Lower Level
);
Modules &
HA_GateLevel HAB2 (
Port module HA_GateLevel(
.a(c_in),
Connection input a, b ,
.b(s1), output c_o, s_o
(2001) );
.c_o(c2), xor (s_o,a,b);
.s_o(sum) and (c_o,a,b);
endmodule
);

Module Logic or(cout,c2,c1);


Comb./Seq.

End Module endmodule


module FA(
Module
input a,b,c_in,
Declaration &
output sum, cout
Port Listing
);
Intermediate
Connections, Wire wire s1,c1,c2;
Declarations
HA_GateLevel HAB1 (
.a(a), //1995 Instantiation Style
.b(b),
Instantiation
.c_o(c1), HA_GateLevel HAB1 (a, b, c1, s1);
of
.s_o(s1)
Lower Level
);
Modules &
HA_GateLevel HAB2 ( // Second Half Adder
Port
.a(c_in), HA_GateLevel HAB2 (c_in, s1, c2, sum );
Connection
.b(s1),
(2001)
.c_o(c2),
.s_o(sum)
);

Module Logic or(cout,c2,c1);


Comb./Seq.

End Module endmodule


4-Bit Full Adder instantiating from 1-bit full
adder

module four_bit_adder(Sum, Cout, A, B, Cin);


// I/O port declarations
output [3:0] Sum; output Cout;
input [3:0] A, B; input Cin;
wire c1, c2, c3; // Internal nets
// Instantiate four 1-bit full adders.
FA FA0(.a(A[0]), .b(B[0]), .cin(Cin), .sum(Sum[0]), .cout(c1));
FA FA1(.a(A[1]), .b(B[1]), .cin(c1), .sum(Sum[1]), .cout(c2));
FA FA2(.a(A[2]), .b(B[2]), .cin(c2), .sum(Sum[2]), .cout(c3));
FA FA3(.a(A[3]), .b(B[3]), .cin(c3), .sum(Sum[3]), .cout(Cout));
endmodule
Design Heirarchy

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