Chapter 3 Third Week 2021
Chapter 3 Third Week 2021
William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 3
A Top-Level View of Computer
Function and Interconnection
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Computer Components
Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton
Hardwired program
The result of the process of connecting the various components in the
desired configuration
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Hardwired Program Concept
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A sequence of codes or instructions
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Part of the hardware interprets each instruction and generates control signals
Provide a new sequence of codes for each new program instead of rewiring
I/O
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the hardware
Components
Major components:
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CPU
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Instruction interpreter
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Module of general-purpose arithmetic and logic functions (ALU & CU)
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I/O Components
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Input module
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Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system
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Output module
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Means of reporting results
The Control Unit and the Arithmetic
and Logic Unit constitute the Central
Processing Unit
Main memory
Temporary storage is needed for code/
instruction and results
Action Categories
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Data transferred to or
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Data transferred
from a peripheral
from processor to
device by transferring
memory or from
between the processor
memory to processor and an I/O module
Processor- Processor-
memory I/O
Data
Control
processing
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An instruction may ●
The processor
specify that the may perform some
sequence of arithmetic or logic
execution be altered operation on data
Computer
Components:
Top Level
View
Memory address Memory buffer MEMORY
register (MAR) register (MBR)
Specifies the Contains the data
address in to be written into
memory or
memory for the
receives the data
next read or
read from
write memory
MAR
Increment PC
Unless told otherwise
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above
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Question
Disable interrupts
Processor will ignore further interrupts while processing one interrupt
Interrupts remain pending and are checked after first interrupt has been
processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to
previous interrupt
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Connecting
Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer
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Input/Output Connection(2)
Bus
characteristic
characteristic is
is that
that it
it is
is aa If
If two
two devices
devices transmit
transmit during
during the
the
dd transmission same
same time period their signals will
time period their signals
transmission medium
medium will
overlap and become garbled
overlap and become garbled
lly
lly consists
line
consists of
unication
unication lines
line is
of multiple
lines
is capable
multiple
capable of
of
Computer
Computer systems
number of
number
systems contain
of different
provide
contain aa
different buses
buses that
that
Inter
provide pathways
pathways between
conn
mitting between
mitting signals
signals components
senting components at
at various
various levels
levels of
of
senting binary
binary 11 and
and the
yy 00 the computer
computer system
system hierarchy
hierarchy
System
System bus
A
A bus
bus
bus that
that connects
connects major
major
The
The most
computer
most common
common
computer interconnection
interconnection
ectio
structures
structures are
are based
based on
on the
n
computer the
computer components
components use of one or more system
(processor, use of one or more system
(processor, memory,
memory, I/O)
I/O) buses
buses
Data Bus
Data lines that provide a path for moving data among system
modules
Used to designate the source or Used to control the access and the
destination of the data on the data use of the data and address lines
bus
Because the data and address lines
If the processor wishes to read a are shared by all components there
word of data from memory it must be a means of controlling their
puts the address of the desired use
word on the address lines
Control signals transmit both
Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
Timing signals indicate the validity
of data and address information
a) Synchronous and
b) Asynchronous
Synchronous
Events determined by clock signals
Control Bus includes clock line upon which a clock transmits a regular sequence of
alternating 1s and 0s
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge (transference of data becomes valid by hand shake
signals)
Usually a single cycle for an event
Timing of
Synchronous
Bus Operations
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In this simple example,
For a read operation, the processor issues a read command at the start
of the second cycle. A memory module recognizes the address
and, after a delay of one cycle, places the data on the data lines.
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Contd..
The processor reads the data from the data lines and drops the read
signal.
For a write operation, the processor puts the data on the data lines at
the start of the second cycle
and issues a write command after the data lines have stabilized.
The memory module copies the information from the data lines
during the third clock cycle.
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Asynchronous Timing
Once the data lines have stabilized, the memory module asserts the
acknowledged line to signal the processor that the data are available.
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Once the processor has read the data from the data lines, it de-asserts
the read signal. This causes the memory module to drop the data and
acknowledge lines.
The processor then drops the write signal and the memory module
drops the acknowledge signal.
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Comparison b/w Synchronous and
Asynchronous timing
Synchronous timing is simpler to implement and test. However, it is less
flexible than asynchronous timing.
Because all devices on a synchronous bus are tied to a fixed clock rate, the
system cannot deviate in clock serving time.
With asynchronous timing, a mixture of slow and fast devices, using older
and newer technology, can share a bus.