+

William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 3
A Top-Level View of Computer
Function and Interconnection
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Computer Components
 Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration
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Hardwired Program Concept

 Hardwired systems are inflexible

 General purpose hardware can do different tasks, given correct

control signals

 Instead of re-wiring, supply a new set of control signals

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Hardware
and Software
Approaches
 Software Software

●
A sequence of codes or instructions
●
Part of the hardware interprets each instruction and generates control signals
Provide a new sequence of codes for each new program instead of rewiring
I/O
●

the hardware
Components

Major components:
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●
CPU
●
Instruction interpreter
●
Module of general-purpose arithmetic and logic functions (ALU & CU)
●
I/O Components
●
Input module
●
Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system
●
Output module
●
Means of reporting results
The Control Unit and the Arithmetic
and Logic Unit constitute the Central
Processing Unit

Main memory
Temporary storage is needed for code/
instruction and results
Action Categories

●
Data transferred to or
●
Data transferred
from a peripheral
from processor to
device by transferring
memory or from
between the processor
memory to processor and an I/O module

Processor- Processor-
memory I/O

Data
Control
processing
●
An instruction may ●
The processor
specify that the may perform some
sequence of arithmetic or logic
execution be altered operation on data
 Computer
Components:
Top Level
View
 Memory address Memory buffer MEMORY
register (MAR) register (MBR)
Specifies the Contains the data
address in to be written into
memory or
memory for the
receives the data
next read or
read from
write memory
MAR

I/O buffer register

I/O address (I/OBR)
+ register (I/OAR) Used for the
Specifies a exchange of
particular data between
an I/O module MBR
I/O device and the CPU
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Basic Instruction Cycle
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Instruction Cycle
 At the beginning of each instruction cycle the processor fetches an
instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that

it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The processor interprets the instruction and performs the required

action
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Instruction Cycle State Diagram
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FEtch

 Program Counter (PC) holds address of next instruction to fetch

 Processor fetches instruction from memory location pointed to by PC

 Increment PC
 Unless told otherwise

 Instruction loaded into Instruction Register (IR)

 Processor interprets instruction and performs required actions

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Execute cycle

 Processor-memory
 data transfer between CPU and main memory

 Processor I/O
 Data transfer between CPU and I/O module

 Data processing
 Some arithmetic or logical operation on data

 Control
 Alteration of sequence of operations
 e.g. jump

 Combination of above
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Question

 Consider memory addresses 300, 301,302 having instruction stored

in these addresses 1940, 5941,2941 respectively. Data 0003, 0002
have been stored at the location having address 940 and 941.
Assuming the 0001, 0101, 0010 for the operation code of load, add,
store respectively in this particular example. Initially the values of
accumulator, program counter is null. Start executing instruction in
the order of storing in the memory and show step by step diagram of
execution.
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Interrupts

Mechanism by which other modules (e.g. I/O) may

interrupt normal sequence of processing
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Transfer of Control via Interrupts
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Instruction Cycle With Interrupts
Instruction Cycle State Diagram
With Interrupts
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Interrupt Cycle

 Added to instruction cycle

 Processor checks for interrupt
 Indicated by an interrupt signal

 If no interrupt, fetch next instruction

 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt through Interrupt handler routine by generating ISR (Interrupt Service
Request)
 Restore context and continue interrupted program
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Time Sequence of Multiple Interrupts
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Multiple Interrupts

 Disable interrupts
 Processor will ignore further interrupts while processing one interrupt
 Interrupts remain pending and are checked after first interrupt has been
processed
 Interrupts handled in sequence as they occur

 Define priorities
 Low priority interrupts can be interrupted by higher priority interrupts
 When higher priority interrupt has been processed, processor returns to
previous interrupt
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Connecting

 All the units must be connected

 Different type of connection for different type of unit

 Memory
 Input/Output
 CPU
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Memory Connection

 Receives and sends data

 Receives addresses (of locations)

 Receives control signals

 Read
 Write
 Timing
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Input/Output Connection(1)

 Similar to memory from computer’s viewpoint

 Output
 Receive data from computer
 Send data to peripheral

 Input
 Receive data from peripheral
 Send data to computer
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Input/Output Connection(2)

 Receive control signals from computer

 Send control signals to peripherals

 Receive addresses from computer

 e.g. port number to identify peripheral

 Send interrupt signals (control)

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CPU Connection

 Reads instruction and data

 Writes out data (after processing)

 Sends control signals to other units

 Receives (& acts on) interrupts

 Signals
Signals transmitted
transmitted by by any
any one
one device
device
munication
munication pathway
pathway are
are available
available for
for reception
reception byby all
all
cting
cting two
two or
or more
more devices
devices other
other devices
devices attached
attached toto the
the bus
bus

Bus
characteristic
characteristic is
is that
that it
it is
is aa If
If two
two devices
devices transmit
transmit during
during the
the
dd transmission same
same time period their signals will
time period their signals
transmission medium
medium will
overlap and become garbled
overlap and become garbled

lly
lly consists

line
consists of
unication
unication lines
line is
of multiple
lines
is capable
multiple

capable of
of
Computer
Computer systems
number of
number
systems contain
of different
provide
contain aa
different buses
buses that
that
Inter
provide pathways
pathways between

conn
mitting between
mitting signals
signals components
senting components at
at various
various levels
levels of
of
senting binary
binary 11 and
and the
yy 00 the computer
computer system
system hierarchy
hierarchy

System
System bus
A
A bus
bus
bus that
that connects
connects major
major
The
The most
computer
most common
common
computer interconnection
interconnection
ectio
structures
structures are
are based
based on
on the

n
computer the
computer components
components use of one or more system
(processor, use of one or more system
(processor, memory,
memory, I/O)
I/O) buses
buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the access and the
destination of the data on the data use of the data and address lines
bus
 Because the data and address lines
 If the processor wishes to read a are shared by all components there
word of data from memory it must be a means of controlling their
puts the address of the desired use
word on the address lines
 Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
of data and address information

 Command signals specify operations

to be performed
Bus Interconnection Scheme
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Timing

 Two types of co-ordination of events on bus

a) Synchronous and

b) Asynchronous

 Synchronous
 Events determined by clock signals
 Control Bus includes clock line upon which a clock transmits a regular sequence of
alternating 1s and 0s
 A single 1-0 is a bus cycle
 All devices can read clock line
 Usually sync on leading edge (transference of data becomes valid by hand shake
signals)
 Usually a single cycle for an event
 Timing of
Synchronous
Bus Operations
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In this simple example,

 The processor places a memory address on the address lines during

the first clock cycle and may assert various status lines.

 Once the address lines have stabilized, the processor

issues an address enable signal.

 For a read operation, the processor issues a read command at the start
of the second cycle. A memory module recognizes the address

 and, after a delay of one cycle, places the data on the data lines.
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Contd..

 The processor reads the data from the data lines and drops the read
signal.

 For a write operation, the processor puts the data on the data lines at
the start of the second cycle

 and issues a write command after the data lines have stabilized.

 The memory module copies the information from the data lines
during the third clock cycle.
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Asynchronous Timing

With asynchronous timing, the

occurrence of one event on a bus follows
and depends on the occurrence of a
previous event.
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Asynchronous Timing – Read Diagram
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In this read example of asynchronous
Read diagram
 The processor places address and status signals on the bus.

 After pausing for these signals to stabilize, it issues a read command,

indicating the presence of valid address and control signals.

 The appropriate memory decodes the address and responds by

placing the data on the data line.

 Once the data lines have stabilized, the memory module asserts the
acknowledged line to signal the processor that the data are available.
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 Once the processor has read the data from the data lines, it de-asserts
the read signal. This causes the memory module to drop the data and
acknowledge lines.

 Finally, once the acknowledge line is dropped, the processor

removes the address information.
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Asynchronous Timing – Write Diagram
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A Simple Asynchronous Write
Operation
 The processor places the data on the data line at the same time that it
puts signals on the status and address lines.

 The memory module responds to the write command by copying the

data from the data lines and then asserting the acknowledge line.

 The processor then drops the write signal and the memory module
drops the acknowledge signal.
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Comparison b/w Synchronous and
Asynchronous timing
 Synchronous timing is simpler to implement and test. However, it is less
flexible than asynchronous timing.

 Because all devices on a synchronous bus are tied to a fixed clock rate, the
system cannot deviate in clock serving time.

 With asynchronous timing, a mixture of slow and fast devices, using older
and newer technology, can share a bus.

 Synchronous connection every device is going to be served whether it had

something to send or not.
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