The ARM Cortex-M3 Processor

Architecture Part-1

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 Module Syllabus
 ARM Architectures and Processors
 What is ARM Architecture

 ARM Processor Families

 ARM Cortex-M Series

 Cortex-M3 Processor

 ARM Processor vs. ARM Architectures

 ARM Cortex-M3 Processor

 Cortex-M3 Processor Overview

 Cortex-M3 Block Diagram

 Cortex-M3 Registers

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 ARM Architectures and
Processors

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 What is ARM Architecture
 ARM architecture is a family of RISC-based processor architectures
 Well-known for its power efficiency;
 Hence widely used in mobile devices, such as smartphones and tablets
 Designed and licensed to a wide eco-system by ARM

 ARM Holdings
 The company designs ARM-based processors;
 Does not manufacture, but licenses designs to semiconductor partners who add their
own Intellectual Property (IP) on top of ARM’s IP, fabricate and sell to customers;
 Also offer other IP apart from processors, such as physical IPs, interconnect IPs,
graphics cores, and development tools.

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 ARM Processor Families
 Cortex-A series (Application) Cortex-A57
Cortex-A53
 High performance processors capable of full
Operating System (OS) support; Cortex-A15

 Applications include smartphones, digital TV, smart

Cortex-A9 Cortex-A
Cortex-A8
books, home gateways etc. Cortex-A7
 Cortex-R series (Real-time) Cortex-A5

 High performance for real-time applications; Cortex-R7

 High reliability Cortex-R5

Cortex-R4
Cortex-R
 Applications include automotive braking system, Cortex-M4
powertrains etc.
Cortex-M3
 Cortex-M series (Microcontroller) Cortex-M1 Cortex-M
Cortex-M0+
 Cost-sensitive solutions for deterministic Cortex-M0
microcontroller applications;
SC000
 Applications include microcontrollers, mixed signal
devices, smart sensors, automotive body electronics
SC100
SC300
SecurCore
and airbags;
ARM11
 SecurCore series ARM9
Classic
 High security applications. ARM7

 Previous classic processors

 Include ARM7, ARM9, ARM11 families As of Dec 2013

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 Design an ARM-based SoC
 Select a set of IP cores from ARM and/or other third-party IP vendors
 Integrate IP cores into a single chip design
 Give design to semiconductor foundries for chip fabrication

IP libraries SoC
Cortex-A9 Cortex-R5 Cortex-M3 ARM
ROM RAM
processor
ARM7 ARM9 ARM11
System bus ARM-based
DRAM ctrl FLASH ctrl SRAM ctrl SoC
Peripherals
AXI bus AHB bus APB bus

GPIO I/O blocks Timer

External Interface

Licensable IPs SoC Design Chip Manufacture

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 ARM Cortex-M Series
 Cortex-M series: Cortex-M0, M0+, M1, M3, M4.
 Energy-efficiency
 Lower energy cost, longer battery life

 Smaller code
 Lower silicon costs

 Ease of use
 Faster software development and reuse

 Embedded applications
 Smart metering, human interface devices, automotive and industrial control systems,
white goods, consumer products and medical instrumentation

As of Dec 2013

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 ARM Processors vs. ARM
Architectures
 ARM architecture
 Describes the details of instruction set, programmer’s model, exception model, and memory map
 Documented in the Architecture Reference Manual
 ARM processor
 Developed using one of the ARM architectures
 More implementation details, such as timing information
 Documented in processor’s Technical Reference Manual

ARMv4/v4T ARMv5/ v4E ARMv6 ARMv7 ARMv8

Architecture Architecture Architecture Architecture ARMv7-A Architecture ARMv8-A
e.g. Cortex-A9 e.g. Cortex-A53
Cortex-A57
ARMv7-R
e.g. Cortex-R4 ARMv8-R

ARM v6-M ARMv7-M

e.g. Cortex-M0, M1 e.g. Cortex-M3

e.g. ARM7TDMI e.g. ARM9926EJ-S e.g. ARM1136

As of Dec 2013
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 ARM Cortex-M Series Family
ARM Core Hardware Hardware Saturated DSP Floating
Processor Thumb® Thumb®-2
Architecture Architecture Multiply Divide Math Extensions Point

Von 1 or 32
Cortex-M0 ARMv6-M Most Subset No No No No
Neumann cycle

Von 1 or 32
Cortex-M0+ ARMv6-M Most Subset No No No No
Neumann cycle

Von 3 or 33
Cortex-M1 ARMv6-M Most Subset No No No No
Neumann cycle

Cortex-M3 ARMv7-M Harvard Entire Entire 1 cycle Yes Yes No No

Cortex-M4 ARMv7E-M Harvard Entire Entire 1 cycle Yes Yes Yes Optional

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 ARM Cortex-M3 Processor
Overview

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 Cortex-M3 Processor Overview
 Cortex-M3 Processor
 Introduced in 2004
 Updated with new technologies and configurability
 The mainstream ARM processor developed specifically with microcontroller
applications in mind

 High Performance Efficiency

 > 1 DMIPS/MHz (Dhrystone Million Instructions Per Second / MHz) at the order of
µWatts / MHz

 Low Power Consumption

 Longer battery life – especially critical in mobile products

 Enhanced Determinism
 The critical tasks and interrupt routines can be served quickly in a known number of
cycles

 Lower Cost
 Reduced 32-bit-based system cost, close to those legacy 8-bit and 16-bit devices (e.g.
can be priced at less than $1)

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 Cortex-M3 Processor Features
 32-bit Reduced Instruction Set Computing (RISC) processor
 Harvard architecture
 Separated data bus and instruction bus

 Instruction set
 Include the entire Thumb®-1 (16-bit) and Thumb®-2 (16/ 32-bit) instruction sets

 3-stage pipeline
 Performance efficiency
 1.25 – 1.89 DMIPS/MHz (Dhrystone Million Instructions Per Second / MHz)

 Supported Interrupts
 Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
 8 to 256 interrupt priority levels

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 Cortex-M3 Processor Features
 Supports Sleep Modes
 Up to 240 Wake-up Interrupts
 Integrated WFI (Wait For Interrupt) and WFE (Wait For Event) Instructions and Sleep On Exit
capability (to be covered in more detail later)

 Sleep & Deep Sleep Signals

 Enhanced Instructions
 Hardware Divide (2-12 Cycles)
 Single-Cycle (32x32) Multiply
 Saturated Math Support
 Debug
 Optional JTAG & Serial-Wire Debug (SWD) Ports
 Up to 8 Breakpoints and 4 Watchpoints
 Memory Protection Unit (MPU)
 Optional 8 region MPU with sub regions and background region

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 Cortex-M3 Processor Features
 Cortex-M3 processor is designed to meet the challenges of low dynamic
power constraints while retaining light footprints
 180 nm ultra low power process –149 µW/MHz
 90 nm low power process – 32 µW/MHz
 40 nm G process – 7 µW/MHz

ARM Cortex-M3 Implementation Data

180ULL 90LP 40G
Process (7-track, typical 1.8v, (7-track, typical 1.2v, 9-track, typical 0.9v,
25C) 25C) 25C)

Dynamic Power 149 µW/MHz 32 µW/MHz 7 µW/MHz

Floorplanned Area 0.43 mm2 0.12 mm2 0.03 mm2

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 Cortex-M3 Block Diagram
ARM Cortex-M3 Microprocessor

Interrupt Processor core

Requests
and NMI

Trace interface
Interrupt Controller
Register

Instruction

Instruction
Fetch unit
Nested Vector

decoder
bank
Debug
(NVIC) ALU
Subsystem

Wakeup Memory interface

Interrupt
Power Controller
management (WIC) Instruction Memory Data
interface bus protection unit bus

Bus interconnect

Program Memory system

memory & peripherals

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 Cortex-M3 Block Diagram
 Processor core
 Contains internal registers, the ALU, data path, and some control logic
 Registers include sixteen 32-bit registers for both general and special usage
 Processor pipeline stages
 Three-stage pipeline: fetch, decode, and execution
 Some instructions may take multiple cycles to execute, in which case the pipeline will
be stalled
 The pipeline will be flushed if a branch instruction is executed

Instruction 1 Fetch Decode Execute

Instruction 2 Fetch Decode Execute

Instruction 3 Fetch Decode Execute

Instruction 4 Fetch Decode Execute

Time

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 Cortex-M3 Block Diagram
 Nested Vectored Interrupt Controller (NVIC)
 Up to 240 interrupt request signals and a non-maskable interrupt (NMI)
 Automatically handles nested interrupts, such as comparing priorities between interrupt
requests and the current priority level

 Wakeup Interrupt Controller (WIC)

 For low-power applications, the microcontroller can enter sleep mode by shutting down
most of the components.
 When an interrupt request is detected, the WIC can inform the power management unit
to power up the system.

 Memory Protection Unit (optional)

 Used to protect memory content, e.g. make some memory regions read-only or
preventing user applications from accessing privileged application data

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 Cortex-M3 Block Diagram
 Bus interconnect
 Allows data transfer to take place on different buses simultaneously
 Provides data transfer management, e.g. a write buffer, bit-oriented operations (bit-
band)
 May include bus bridges (e.g. AHB-to-APB bus bridge) to connect different buses into a
network using a single global memory space
 Includes the internal bus system, the data path in the processor core, and the AHB
LITE interface unit

 Debug subsystem
 Handles debug control, program breakpoints, and data watchpoints
 When a debug event occurs, it can put the processor core in a halted state, where
developers can analyse the status of the processor at that point, such as register
values and flags

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 ARM Cortex-M3 Processor
Registers

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 Cortex-M3 Registers
 Processor registers
 The internal registers are used to store and process temporary data within the
processor core
 All registers are inside the processor core, hence they can be accessed
quickly
 Load-store architecture
 To process memory data, they have to be first loaded from memory to
registers, processed inside the processor core using register data only,
and then written back to memory if needed

 Cortex-M3 registers
 Register bank
 Sixteen 32-bit registers (thirteen are used for general-purpose);
 Special registers

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 Cortex-M3 Registers
Register bank R0
R1
R2
R3
Low
R4 Registers

R5
General purpose
R6
register
R7
R8
R9
R10 High
Registers
R11
R12 MSP
Stack Pointer (SP) R13(banked) Main Stack Pointer

Link Register (LR) R14 PSP

Program Counter (PC) R15 Process Stack Pointer

Special registers Program Status Registers (PSR) x PSR APSR EPSR IPSR
PRIMASK Application Execution Interrupt
PSR PSR PSR
Interrupt mask register FAULTMASK
BASEPRI
Stack definition CONTROL

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 Cortex-M3 Registers
 R0 – R12: general purpose registers
 Low registers (R0 – R7) can be accessed by any instruction Data Data
 High registers (R8 – R12) sometimes cannot be accessed e.g.
by some Thumb (16-bit) instructions PUSH POP

 R13: Stack Pointer (SP) Low

 Records the current address of the stack

Stack Address
 Used for saving the context of a program while switching
between tasks SP
 Cortex-M3 has two SPs: Main SP, used in applications that High
PC
require privileged access e.g. OS kernel, and exception
handlers, and Process SP, used in base-level application Heap
code (when not running an exception handler)
 Program Counter (PC)
 Records the address of the current instruction code
 Automatically incremented by 4 at each operation (for 32-bit Code
instruction code), except branching operations
 A branching operation, such as function calls, will change the
PC to a specific address, meanwhile it saves the current PC to
the Link Register (LR)

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 Cortex-M3 Registers
 R14: Link Register (LR)
 The LR is used to store the return address of a subroutine or a
function call
 The program counter (PC) will load the value from LR after a
function is finished

Current PC Current LR
PC LR
1. Save current Main Main
PC to LR Program Program
Code region

code Load PC with the code

Code region
LR
address in LR to
return to the
2. Load PC with main program
the starting
address of the
subroutine subroutine
subroutine Current PC
PC

Call a subroutine Return from a subroutine to the main program

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 Cortex-M3 Registers
 xPSR, combined Program Status Register
 Provides information about program execution and ALU flags
 Application PSR (APSR)
 Interrupt PSR (IPSR)
 Execution PSR (EPSR)

APSR NZ CV Q Reserved

IPSR Reserved ISR number

EPSR ICI/IT T Reserved ICI/IT

xPSR N Z C V Q ICI/IT T Reserved ICI/IT ISR number

bit31 bit24 bit16 bit8 bit0

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 Cortex-M3 Registers
 APSR
 N: negative flag – set to one if the result from ALU is negative
 Z: zero flag – set to one if the result from ALU is zero
 C: carry flag – set to one if an unsigned overflow occurs
 V: overflow flag – set to one if a signed overflow occurs
 Q: sticky saturation flag – set to one if saturation has occurred in saturating arithmetic
instructions, or overflow has occurred in certain multiply instructions

 IPSR
 ISR number – current executing interrupt service routine number

 EPSR
 T: Thumb state – always one since Cortex-M3 only supports the Thumb state (more on
processor states in the next module)
 IC/IT: Interrupt-Continuable Instruction (ICI) bit, IF-THEN instruction status bit

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 Cortex-M3 Registers
 Interrupt mask registers
 1-bit PRIMASK
 Set to one will block all the interrupts apart from nonmaskable interrupt (NMI) and the hard
fault exception

 1-bit FAULTMASK
 Set to one will block all the interrupts apart from NMI
 1-bit BASEPRI
 Set to one will block all interrupts of the same or lower level (only allow for interrupts with
higher priorities)

 CONTROL: special register

 1-bit stack definition
 Set to one: use the process stack pointer (PSP)
 Clear to zero: use the main stack pointer (MSP)

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 Cortex-M3 Registers

PRIMASK

PRIMASK Reserved

FAULTMASK

FAULTMASK Reserved

BASEPRI

BASEPRI Reserved

CONTROL Reserved

bit31 bit24 bit16 bit8

Stack definition

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 Useful Resources
 Reference1
 Book: “The Definitive Guide to the ARM Cortex-M3” by Joseph Yiu, ISBN-10:
0123854776, ISBN-13: 978-1856179638, 12 Jan 2010

 Reference2
 ARM v7-M Architecture Reference Manual:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html

 Reference3
 Cortex-M3 Technical Reference Manual:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/index.html

 Reference4
 Cortex-M3 Devices Generic User Guide:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf

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