Computer-System Structures

BY
[email protected]

COMSATS Institute of Information Technology,

Lahore
Computer System Structure
 Computer-System Operation
 I/O Structure
 Storage Structure
 Storage Hierarchy
 Hardware Protection
 General System Architecture

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Computer-System Architecture

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Computer-System Operation
 I/O devices and the CPU can execute concurrently.
 Each device controller is in charge of a particular
device type.
 Each device controller has a local buffer.
 CPU moves data from/to main memory to/from the
local buffers.
 I/O is from the device to local buffer of controller.
 Device controller informs CPU that it has finished
its operation by causing an interrupt.

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Interrupts
 An interruption of the normal sequence of
execution
 Improves processing efficiency
 Allows the processor to execute other
instructions while an I/O operation is in
progress
 A suspension of a process caused by an event
external to that process and performed in such
a way that the process can be resumed

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Classes of Interrupts
 Program
 arithmetic overflow
 division by zero
 execute illegal instruction
 reference outside user’s memory space
 Timer
 I/O
 Hardware failure

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Interrupt Handler
 A program that determines nature of
the interrupt and performs whatever
actions are needed
 Control is transferred to this program
 Generally part of the operating
system

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Multiple Interrupts
 Disable interrupts
while an interrupt is
being processed
 Processor ignores
any new interrupt
request signals

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Multiple Interrupts
Sequential Order
 Disable interrupts so processor can
complete task
 Interrupts remain pending until the
processor enables interrupts
 After interrupt handler routine
completes, the processor checks for
additional interrupts

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Multiple Interrupts
Priorities
 Higher priority interrupts cause
lower-priority interrupts to wait
 Causes a lower-priority interrupt
handler to be interrupted
 Example when input arrives from
communication line, it needs to be
absorbed quickly to make room for
more input

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Common Functions of Interrupts
 Interrupt transfers control to the interrupt service
routine, generally, through the interrupt vector, which
contains the addresses of all the service routines.
 Interrupt architecture must save the address of the
interrupted instruction.
 Incoming interrupts are disabled while another
interrupt is being processed to prevent a lost
interrupt.
 A trap is a software-generated interrupt caused
either by an error or a user request.
 An operating system is interrupt driven.

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Interrupt Handling

 The operating system preserves the state of

the CPU by storing registers and the program
counter.
 Separate segments of code determine
what action should be taken for each
type of interrupt.

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Interrupt Handling
 Determines which type of interrupt has
occurred:
 vectored interrupt system
 Interrupt vector
 Polling
 Bus interrupt priority level(IPL)
 Interrupt request number (IRQ)

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I/O Structure
 Synchronous I/O - After I/O starts, control returns to user
program only upon I/O completion.
 Wait instruction idles the CPU until the next interrupt.
 Wait loop
 At most one I/O request is outstanding at a time, no
simultaneous I/O processing.
 Asynchronous I/O - After I/O starts, control returns to user
program without waiting for I/O completion.
 System call – request to the operating system to allow user
to wait for I/O completion.
 Device-status table contains entry for each I/O device
indicating its type, address, and state.
 Operating system indexes into I/O device table to
determine device status and to modify table entry to
include interrupt.

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Two I/O Methods
Synchronous Asynchronous

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Device-Status Table

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Direct Memory Access Structure
 Used for high-speed I/O devices able to
transmit information at close to memory
speeds.
 Device controller transfers blocks of data
from buffer storage directly to main
memory without CPU intervention.
 Only one interrupt is generated per
block, rather than the one interrupt per
byte.
Direct Memory Access (DMA)
Structure

Used for high-speed I/O devices able to transmit

information at close to memory speeds.
Device controller transfers blocks of data from buffer
storage directly to main memory without CPU
intervention.
Only one interrupt is generated per block, rather than
the one interrupt per byte (word).

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Step Process to Perform DMA
Transfer

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Storage Structure
 Main memory – only large storage media that the
CPU can access directly.
 Secondary storage – extension of main memory
that provides large nonvolatile storage capacity.
 Magnetic disks – rigid metal or glass platters
covered with magnetic recording material
 Disk surface is logically divided into tracks,
tracks
which are subdivided into sectors.
sectors
 The disk controller determines the logical
interaction between the device and the
computer.

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Magnetic Disk Structure
 A hard disk consists of a number of
platters
 Platters can store data on wither one or both of
its surfaces so is referred to as
 Single-sided or double sided
 Each surface is composed of concentric
rings called tracks
 The set of all tracks with the same diameter is
called a cylinder
 Tracks are divided into arcs called sectors

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Magnetic Disk Structure
 Data is transferred to or from a surface by
a disk head
 There is one disk head for each surface
 These disk heads are moved as a unit (called a
disk head array)
 All the heads are in an identical position with
regard to which track they are over
 To read or write a block a disk head must be
positioned over it

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Measurements of Performance
 Seek time
 is the time for the disk are to move the heads to
the cylinder containing the desired sector.
 Rotation delay or latency time
 is the additional time waiting for the disk to rotate
the desired sector to the disk head.
 Random Access time(Positioning time)
 The sum of seek time and rotation delay
 Transfer rate
 The transfer date is the rate at which data flow
between the drive and the computer

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Moving-Head Disk Mechanism
head
sector

platter
track
cylinder

surfaces

spindle
actuator

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Disk Anatomy

disk head
array

track

platters
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Magnetic Tapes

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Storage Hierarchy
 Storage systems organized in hierarchy.
 Speed
 Cost
 Volatility
 Speed of magnetic disk
 transfer rate * size
 positioning time (random access time)
 seek time + rotational latency
 Caching – copying information into faster
storage system; main memory can be viewed as
a fast cache for secondary storage

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Storage-Device Hierarchy

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Caching
 Important principle, performed at many levels in a
computer (in hardware, operating system, software)
 Information in use copied from slower to faster storage
temporarily
 Faster storage (cache) checked first to determine if
information is there
 If it is, information used directly from the cache
(fast)
 If not, data copied to cache and used there
 Since caches has limited size, cache management is an
important design problem
 Cache size and replacement policy

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Hardware Protection
 Dual-Mode Operation
 I/O Protection
 Memory Protection
 CPU Protection

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Dual-Mode Operation
 Sharing system resources requires OS to
ensure that an incorrect program cannot cause
other programs to execute incorrectly
 Provide hardware support to differentiate
between at least two modes of operations
1. User mode – execution done on behalf of a
user
2. Monitor mode (also supervisor mode or
system mode) – execution done on behalf of
operating system

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Dual-Mode Operation
 Mode bit added to computer hardware to
indicate the current mode: monitor (0) or user
(1)
 When an interrupt or fault occurs hardware
switches to monitor mode
Interrupt/fault

monitor user

set user mode

Privileged instructions can be issued only in monitor mode

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I/O Protection
 All I/O instructions are privileged
instructions
 Must ensure that a user program could
never gain control of the computer in
monitor mode.

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Use of A System Call to Perform
I/O

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Memory Protection
 Must provide memory protection at least for
the interrupt vector and the interrupt service
routines
 In order to have memory protection, add two
registers that determine the range of legal
addresses a program may access:
 Base register – holds the smallest legal
physical memory address
 Limit register – contains the size of the
range
 Memory outside the defined range is protected

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Example of Memory Protection

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Protection Hardware

When executing in monitor mode, the operating system has

unrestricted access to both monitor and users’ memory.
 The load instructions for the base and limit registers are privileged
instructions.
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CPU Protection
 Timer – interrupts computer after specified
period to ensure operating system maintains
control
 Timer is decremented every clock tick
 When timer reaches the value 0, an
interrupt occurs
 Timer commonly used to implement time
sharing
 Time also used to compute the current time.
 Load-timer is a privileged instruction

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