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Computer Architecture: Pipelining Khiyam Iftikhar

This document discusses computer architecture and pipelining. It explains that pipelining allows instructions to be processed simultaneously across multiple stages, improving performance over a single-cycle architecture where all instructions must wait. Common pipeline hazards like structural hazards caused by shared hardware resources and data hazards caused by instruction dependencies are addressed through techniques like forwarding. Control hazards from branch instructions are handled by predicting branch outcomes or delaying branch execution. Overall pipelining can increase throughput by allowing new instructions to begin processing before previous ones finish.

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Hassan Asghar
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43 views36 pages

Computer Architecture: Pipelining Khiyam Iftikhar

This document discusses computer architecture and pipelining. It explains that pipelining allows instructions to be processed simultaneously across multiple stages, improving performance over a single-cycle architecture where all instructions must wait. Common pipeline hazards like structural hazards caused by shared hardware resources and data hazards caused by instruction dependencies are addressed through techniques like forwarding. Control hazards from branch instructions are handled by predicting branch outcomes or delaying branch execution. Overall pipelining can increase throughput by allowing new instructions to begin processing before previous ones finish.

Uploaded by

Hassan Asghar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Computer Architecture

Pipelining
Khiyam Iftikhar
Why not Single-Cycle
• All instruction take same time
– Clock cycle is equal to worst case delay
– No benefit of making common case fast
Pipelining: Laundry analogy
Performance
• Conlusion: Pipelined is ‘n’ times faster where
‘n’ is number of stages.
MIPS Single Cycle Vs Pipelined
Cycle Time Period
• Cycle time for single cycle is equal to
combined delay of all the sources for the
longest instruction (that requires max time
• Cycle time for pipelined is equal to delay of
the slowest stage.
MIPS Single Cycle Vs Pipelined
Cycle Time Period
Designing instruction set for Pipelining
MIPS was designed for pipelining
• All instructions are of same length.
– So 1 fetch stage.
• All instruction have source registers at the same place
– So 1 decode stage.
– So instruction is decoded at the same time when the operands are fetched
from registers.
• Memory is accessed only in lw and sw
– If it was allowed to operate on memory, execute stage should be split to three
stages, address calculation, memory access, execute.
• Operands must be aligned in memory.
– So a single data transfer requires one memory access; otherwise two
accesses are required.
Pipeline Hazards: Structural
• Hardware doesn’t support combination of
instructions that are executed in a clock cycle

• Example:
– Single Data and instruction memory
– Lw is WriteBack Stage
Data Hazard
• Operands of an instruction depend upon
result of previous instruction

• Without forwarding it results in delay of 2


clock cycles between the two instructions.
• Solution: Data Forwarding (Bypassing)
Hazard Types
Delaying Instruction Issue
Type 1 Dependency
Delaying Instruction Issue
Type 2 Dependency

1 cycle delay
Example:Pipelined Datapath cycle by cycle
detail
Solution
• No of stalls without forwarding is 2
• Reordered code is
Pipelined Datapath R-type,lw/sw,branch
Datapath with Forwarding Unit
Resolving Data Hazards:
Data Forwarding Type 1
Resolving Data Hazards:
Data Forwarding Type 2
Example :Dependency detection
Cases Where even Data Forwarding creates a Stall (Bubble)

If lw is followed by a depending instruction


Hazard Detection Unit
Hazard Detection Unit
Control Hazards
• Caused by branch instructions
– Because Branch result modifies PC
• Without any arrangement Branch will result in a
stall of 3 cycles.
• Methods to handle
– Extra Hardware to calculate Branch result and
address
– Prediction
– Delayed Execution
Pipelined Datapath R-type,lw/sw,branch
Effect on Performance
Extra Hardware
• If we add extra hardware so that registers
comparison and address calculation is
performed during 2nd stage. The result is
written to PC in third stage
• Even with this arrangement 1 bubble is added
Branch in Pipeline with Extra Hardware
Branch Prediction:
Branch not Taken
• Instead of waiting for branch result, Fetch next
instruction based on prediction.
• If the prediction is right, no bubble is added
otherwise the instruction is flushed and a
bubble is added

• Simplest Implementation: Branch not taken


Dynamic Branch Prediction
• Maintain history for each branch for multiple
instances.
• Then predict on the basis of recent past
behavior.
Dynamic (4 state) Branch Predictor

It changes state from ‘Predict Not Taken’ to ‘Predict Taken’ after 2 consecutive Taken
Delayed Execution
• Place an instruction which is not effected by
result of branch, after branch instruction

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