UNIT IV

HARDWARE ACCELERATES &

NETWORKS
Accelerators – Accelerated system design –
Distributed Embedded Architecture –Networks for
Embedded Systems – Network based design – Internet
enabled systems
 Accelerators
Why multiprocessors?
Better real-time performance.
Put time-critical functions on less-loaded processing
elements.
Remember RMS utilization---extra CPU cycles must be
reserved to meet deadlines.

cost
deadline w.
deadline RMS overhead
performance
Accelerated systems
Use additional computational unit dedicated to some
functions?
Hardwired logic.
Extra CPU.
Hardware/software co-design: joint design of
hardware and software architectures.
Accelerated system architecture
request
accelerator
result
datadata
CPU
memory

I/O
Accelerator vs. co-processor
A co-processor executes instructions.
Instructions are dispatched by the CPU.
An accelerator appears as a device on the bus.
The accelerator is controlled by registers.

IMPLEMENTATIONS
Application-specific integrated circuit.
Field-programmable gate array (FPGA).
Standard component.
Example: graphics processor.
 Network elements
distributed computing platform:

PE
PE

communication link

network

PE
PEs may be CPUs or ASICs.
Networks in embedded systems
initial processing

more processing

PE sensor
PE

PE actuator
Why distributed?
Higher performance at lower cost.
Physically distributed activities---time constants may
not allow transmission to central site.
Improved debugging---use one CPU in network to
debug others.
May buy subsystems that have embedded processors.
Network abstractions
International Standards Organization (ISO)
developed the Open Systems Interconnection (OSI)
model to describe networks:
7-layer model.
Provides a standard way to classify network
components and operations.
OSI model
application end-use interface

presentation data format

session application dialog control

transport connections

network end-to-end service

data link reliable data transport

physical mechanical, electrical

OSI layers
Physical: connectors, bit formats, etc.
Data link: error detection and control across a single
link (single hop).
Network: end-to-end multi-hop data communication.
Transport: provides connections; may optimize
network resources.
Session: services for end-user applications: data
grouping, checkpointing, etc.
Presentation: data formats, transformation services.
Application: interface between network and end-user
programs.
Hardware architectures
Many different types of networks:
topology;
scheduling of communication;
routing.
Point-to-point networks
One source, one or more destinations, no data
switching (serial port):

PE 1 PE 2 PE 3

link 1 link 2
Bus networks
Common physical connection:

PE 1 PE 2 PE 3 PE 4

header address data ECC packet format

 Bus arbitration
Fixed: Same order of resolution every time.
Fair: every PE has same access over long periods.
round-robin: rotate top priority among Pes.

fixed A B C A B C

round-robin
A B C B C A

A,B,C A,B,C
Crossbar
out4

out3

out2

out1

in1 in2 in3 in4

Crossbar characteristics
Non-blocking.
Can handle arbitrary multi-cast combinations.
Size proportional to n2.
Multi-stage networks
Use several stages of switching elements.
Often blocking.
Often smaller than crossbar.
Message-based programming
Transport layer provides message-based programming
interface:
send_msg(adrs,data1);
Data must be broken into packets at source,
reassembled at destination.
Data-push programming: make things happen in
network based on data transfers.
I2C bus
Designed for low-cost, medium data rate applications.
Characteristics:
serial;
multiple-master;
fixed-priority arbitration.
Several microcontrollers come with built-in I2C
controllers.
I2C physical layer
master 1 master 2
data line
SDL

clock line
SCL

slave 1 slave 2
I2C data format
SCL ...
...

...
SDL

start MSB ack

I2C electrical interface
Open collector interface: +

SDL

SCL
I2C signaling
Sender pulls down bus for 0.
Sender listens to bus---if it tried to send a 1 and heard
a 0, someone else is simultaneously transmitting.
Transmissions occur in 8-bit bytes.

I2C data link layer

Every device has an address (7 bits in standard, 10 bits
in extension).
Bit 8 of address signals read or write.
General call address allows broadcast.
I2C bus arbitration
Sender listens while sending address.
When sender hears a conflict, if its address is higher, it
stops signaling.
Low-priority senders relinquish control early enough
in clock cycle to allow bit to be transmitted reliably.
I2C transmissions
multi-byte write

S adrs 0 data data P

read from slave

S adrs 1 data P

write, then read

S adrs 0 data S adrs 1 data P

Ethernet
Dominant non-telephone LAN.
Versions: 10 Mb/s, 100 Mb/s, 1 Gb/s
Goal: reliable communication over an unreliable
medium.

Ethernet topology
Bus-based system, several possible physical layers:

A B C
CSMA/CD
Carrier sense multiple access with collision detection:
sense collisions;
exponentially back off in time;
retransmit.

Exponential back-off times

time
Ethernet packet format

start source dest data

preamble length padding CRC
frame adrs adrs payload
Ethernet performance
Quality-of-service tends to non-linearly decrease at
high load levels.
Can’t guarantee real-time deadlines. However, may
provide very good service at proper load levels.
Fieldbus
Used for industrial control and instrumentation---
factories, etc.
H1 standard based on 31.25 MB/s twisted pair
medium.
High Speed Ethernet (HSE) standard based on 100
Mb/s Ethernet.
Networks
Network-based design.
Communication analysis.
System performance analysis.
Internet.
Internet-enabled systems.
Vehicles as networks.
Sensor networks
Communication analysis
First, understand delay for single message.
Delay for multiple messages depends on:
network protocol;
devices on network.
Message delay
Assume:
single message;
no contention.
Delay:
tm = tx + tn + tr
 = xmtr overhead + network xmit time + rcvr overhead
Example: I2C message delay
Network transmission time dominates.
Assume 100 kbits/sec, one 8-bit byte.
Number of bits in packet:
npacket = start + address + data + stop
 = 1 + 8 + 8 + 1 = 18 bits
Time required to transmit: 1.8 x 10-4 sec.
20 instructions on 8 MHz controller adds 2.5 x 10-6
delay on xmtr, rcvr.
Multiple messages
If messages can interfere with each other, analysis is
more complex.
Model total message delay:
ty = td + tm
 = wait time for network + message delay
Arbitration and delay
Fixed-priority arbitration introduces unbounded delay
for all but highest-priority device.
Unless higher-priority devices are known to have limited
rates that allow lower devices to transmit.
Round-robin arbitration introduces bounded delay
proportional to N.
Priority inversion in networks
In many networks, a packet cannot be interrupted.
Result is priority inversion:
low-priority message holds up higher-priority message.
Doesn’t cause deadlock, but can slow down important
communications.
Multihop networks
In multihop networks, one node receives message,
then retransmits to destination (or intermediate).

hop 1 hop 2

A B C
Network 1 Network 2
System performance analysis
System analysis is difficult in general.
multiprocessor performance analysis is hard;
communication performance analysis is hard.
Simple example: uncertainty in P1 finish time ->
uncertainty in P2 start time.

P1 P2
Analysis challenges
P2 and P3 can delay each other, even though they are
P1
in separate tasks.
Delays in P1 propagate to P2, then P3, then to P4.
P2

P3

P4
Lower bounds on system
Communication
Computational requirements:
requirements:
Count
sum upall
process
transmissions
requirements
in oneover
period.
least-common
multiple of periods, average over one period.
Hardware platform design
Need to choose:
number and types of PEs;
number and types of networks.
Evaluate a platform by allocating processes,
scheduling processes and communication.
I/O-intensive systems
Start with I/O devices, then consider computation:
inventory required devices;
identify critical deadlines;
chooses devices that can share PEs;
analyze communication times;
choose PEs to go with devices.
Computation-intensive systems
Start with shortest-deadline tasks:
Put shortest-deadline tasks on separate PEs.
Check for interference on critical communications.
Allocate low-priority tasks to common PEs wherever
possible.
Balance loads wherever possible.
Internet Protocol
Internet Protocol (IP) is basis for Internet.
Provides an internetworking standard: between two
Ethernets, Ethernet and token ring, etc.
Higher-level services are built on top of IP.
IP in communication
application application

presentation presentation

session session
IP
transport transport

network network network

data link data link data link

physical physical physical

node A router
node B
IP packet
Includes:
version, service type, length
time to live, protocol
source and destination address
data payload
Maximum data payload is 65,535 bytes.
IP addresses
32 bits in early IP, 128 bits in IPv6.
Typically written in form xxx.xx.xx.xx.
Names (foo.baz.com) translated to IP address by
domain name server (DNS).
Internet routing
Best effort routing:
doesn’t guarantee data delivery at IP layer.
Routing can vary:
session to session;
packet to packet.
Higher-level Internet services
Transmission Control Protocol (TCP) provides
connection-oriented service.
Quality-of-service (QoS) guaranteed services are
under development.
The Internet service stack

FTP HTTP SMTP telnet SNMP

User
TCP UDP Datagram
Protocol

IP
Internet-enabled embedded system
Internet-enabled embedded system: any
embedded system that includes an Internet
interface (e.g., refrigerator).
Internet appliance: embedded system designed for
a particular Internet task (e.g. email).
Examples:
Cell phone.
Laser printer.
Sensor networks
Wireless networks, small nodes.
Ad hoc networks---organizes itself without system
administrator:
Must be able to declare membership in network, find
other networks.
Must be able to determine routes for data.
Must update configuration as nodes enter/leave.
Node capabilities
Must be able to turn radio on/off quickly with low
power overhead.
Communication/computation power = 100x.
Radios should operate at several different power levels
to avoid interference with other nodes.
Must buffer, route network traffic.
CAN bus
First used in 1991.
Serial bus, 1 Mb/sec up to
40 m.
Synchronous bus.
Logic 0 dominates logic 1
on bus.
Arbitrated with
CSMA/AMP:
 Arbitration on message
priority.
CAN data frame
11 bit destination
address.
RTR bit determines
read/write from/to
destination.
Any node can detect
bus error, interrupt
packet for
retransmission.
CAN controller
Controller implements
physical and data link
layers.
No network layer
needed---bus provides
end-to-end connections.
Other vehicle busses
FlexRay is next generation:
Time triggered protocol.
10 Mb/s.
Local Interconnect Network (LIN) connects
devices in a small area (e.g., door).
Passenger entertainment networks:
Bluetooth.
Media Oriented Systems Transport (MOST).