Interrupts (Peripheral - Computer Connections)
Interrupts (Peripheral - Computer Connections)
When interrupt is generated from multiple devices, it is required for the CPU to
determine which interrupt to respond first. There are 2 ways deal with the
interrupts:
Each device is assigned with a vector address (VAD) by a priority interrupt unit
which indicates the priority level of a particular device.
Priority is defined by the speed of a device; a low speed device has low priority
(e.g. keyboard) and a high speed device has high priority (e.g. disk drive).
A high priority device must be serviced first than a low priority device.
Priority Interrupt: Serial or Daisy Chain
It consist of interrupt register whose bits are set separately by the interrupting
devices.
Priority is established according to the position of the bits in the register.
Mask register is used to provide facility for the higher priority devices to interrupt
when lower priority device is being serviced or disable all lower priority devices
when higher is being serviced.
Corresponding interrupt bit and mask bit are ANDed and applied to priority
encoder.
Interrupts for devices are ORed to indicate CPU that an interrupt has occurred.
Priority Interrupt: Parallel
Priority Interrupt: Parallel
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