Scribd
Upload
71 views12 pages

Pipeline: Datahazard, Stall

This document discusses pipeline hazards that can occur in a CPU pipeline and how they are resolved. It covers three main types of hazards: 1) Structural hazards occur when the same hardware resource is needed for two different instructions at the same time. 2) Data hazards happen when an instruction tries to use a value before it is ready, such as dependent instructions. 3) Control hazards involve making a decision before a condition is fully evaluated, like branches. The CPU detects hazards and stalls the pipeline as needed to resolve the hazards, ensuring instructions execute in program order and dependent values are ready when needed. Data hazards in particular are resolved by stalling to insert bubbles between dependent instructions.

Uploaded by

Martin Fuentes Acosta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
71 views12 pages

Pipeline: Datahazard, Stall

This document discusses pipeline hazards that can occur in a CPU pipeline and how they are resolved. It covers three main types of hazards: 1) Structural hazards occur when the same hardware resource is needed for two different instructions at the same time. 2) Data hazards happen when an instruction tries to use a value before it is ready, such as dependent instructions. 3) Control hazards involve making a decision before a condition is fully evaluated, like branches. The CPU detects hazards and stalls the pipeline as needed to resolve the hazards, ensuring instructions execute in program order and dependent values are ready when needed. Data hazards in particular are resolved by stalling to insert bubbles between dependent instructions.

Uploaded by

Martin Fuentes Acosta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 12

Pipelining

Capítulo 6, Hennesy & Patterson

Augusto Salazar
Departamento de Ingeniería de Sistemas
Universidad del Norte
[email protected]

Originalmente por Profesor Miguel Jimeno

Basada en presentaciones de Dr. Soontae Kim, USF, David Brooks, Harvard y


Y en las presentaciones de la Universidad de Texas
1
Can pipelining get us into
trouble?
• Yes: Pipeline Hazards
– structural hazards: attempt to use the same resource two
different ways at the same time
• E.g., combined washer/dryer would be a structural hazard or
folder busy doing something else (watching TV)
– data hazards: attempt to use item before it is ready
• E.g., one sock of pair in dryer and one in washer; can’t fold until
get sock from washer through dryer
• instruction depends on result of prior instruction still in the
pipeline
– control hazards: attempt to make a decision before condition
is evaulated
• E.g., washing football uniforms and need to get proper detergent
level; need to see after dryer before next load in
• branch instructions
• Can always resolve hazards by waiting
– pipeline control must detect the hazard
– take action (or delay action) to resolve hazards
2
Esctructural Hazards

• HW is not able to complete instructions at a given


clock

• MIPS´s design protects us from this hazard


3
Three Generic Data Hazards

• Read After Write (RAW)


InstrJ tries to read operand before InstrI writes it

I: add r1,r2,r3
J: sub r4,r1,r3

• Caused by a “Dependence” (in compiler


nomenclature). This hazard results from an actual
need for communication.

4
Three Generic Data Hazards

• Write After Read (WAR)


InstrJ writes operand before InstrI reads it
I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7

• Called an “anti-dependence” by compiler writers.


This results from reuse of the name “r1”.

• Can’t happen in MIPS 5 stage pipeline because:


– All instructions take 5 stages, and
– Reads are always in stage 2, and
– Writes are always in stage 5
5
Three Generic Data Hazards
• Write After Write (WAW)
InstrJ writes operand before InstrI writes it.

I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
• Called an “output dependence” by compiler writers
This also results from the reuse of name “r1”.
• Can’t happen in MIPS 5 stage pipeline because:
– All instructions take 5 stages, and
– Writes are always in stage 5
• Will see WAR and WAW in more complicated pipes

6
Register Usage Can Cause Data Hazards

7
HW Stalls to Resolve Data Hazard

Time (clock cycles)


I ID/R EX ME WB

ALU
F FReg MDm
I add r1,r2,r3 Im Reg

ALU
s
t
sub r4, r1,r3 Im bubble bubble bubble Reg Dm Reg

r.
and r6,r1,r7

ALU
Im Reg Dm
O
r
or r8,r1,r9

ALU
d Im Reg
e
r Im Reg
xor r10,r1,r11

8
How HW really stalls pipeline
• HW doesn’t change PC => keeps fetching same instruction
& sets control signals to benign values (0)

Time (clock cycles)


I ID/R EX ME WB

ALU
F FReg MDm
I add r1,r2,r3 Im Reg

n
s
t
stall Im bubble bubble bubble bubble

r.
Im
stall bubble bubble bubble bubble
O
r Im bubble bubble bubble bubble
d stall
e
sub r4,r1,r3

ALU
r Im Reg Dm Reg

and r6,r1,r7

ALU
Im Reg Dm

9
Hazard Conditions

EX Hazard

If (EX/MEM.RegWrite
and (EX/MEM.RegisterRd <> 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs

If (EX/MEM.RegWrite
and (EX/MEM.RegisterRd <> 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt

Memory Hazard

If (MEM/WB.RegWrite
and (MEM/WB.RegisterRd <> 0)
and (EX/MEM.RegisterRd <> ID/EX.RegisterRs)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

If (MEM/WB.RegWrite
and (MEM/WB.RegisterRd <> 0)
and (EX/MEM.RegisterRd <> ID/EX.RegisterRt)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))

10
Hazard Conditions

There are also some cases that have to be taken


into consideration:

add $1
sw $4, 0($1)

add $1
sw $1, 0($4)

11
Logisim implementation

Implement over the pipeline 1 the stall detection, it is


important to show the included instructions on the
displays.

With the stalls the results from the RAM of pipeline


should be as expected.

12

You might also like