COMP541

Datapath &
Single-Cycle MIPS

Montek Singh

Mar {5, 7}, 2018

1
Topics
 Complete the datapath
 Add control to it
 Create a full single-cycle MIPS!

 Reading
 Chapter 7
 Review MIPS assembly language
 Chapter 6 of course textbook
 Or, Patterson Hennessy (inside front flap)
A MIPS CPU

reset clk clk

pc memwrite
dataaddr
Instr Data
MIPS CPU writedata
Memory instr Memory
readdata

3
Top-Level: MIPS CPU + memories
Top-level module reset clk

reset clk clk

pc memwrite
dataaddr
Instr Data
MIPS CPU writedata
Memory instr Memory
readdata

We will add I/O devices (display, keyboard, etc.) later

4
One level down: Inside MIPS
 Datapath: components that store or process data
 registers, ALU, multiplexors, sign-extension, etc.
 we will regard memories as outside the CPU, so not part of the core datapath
 Control: components that tell datapath what to do and when
 control logic (FSMs or combinational look-up tables)

MIPS CPU
clk
Control
reset

ALUFN, opcode, memwrite

regwrite, func,
regdst… flagZ … clk
pc
dataadr
Instr MIPS Data
writedata
Memory instr Datapath Memory
readdata
 Review: MIPS instruction types

Three instruction formats:

 R-Type: register operands
 I-Type: immediate operand
 J-Type: for jumps

6
Review: Instruction Formats

R-Type
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits

J-Type
op addr
6 bits 26 bits
R-Type instructions
 Register-type
 3 register operands:
 rs, rt: source registers
 rd: destination register
 Other fields:
 op: the operation code or opcode (0 for R-type instructions)
 funct: the function
– together, op and funct tell the computer which operation to perform
 shamt: the shift amount for shift instructions, otherwise it is 0

R-Type
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type Examples

Assembly Code Field Values

op rs rt rd shamt funct

add $s0, $s1, $s2 0 17 18 16 0 32

sub $t0, $t3, $t5 0 11 13 8 0 34

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Note the order of

registers in the assembly
code:
add rd, rs, rt
Machine Code
op rs rt rd shamt funct

000000 10001 10010 10000 00000 100000 (0x02328020)

000000 01011 01101 01000 00000 100010 (0x016D4022)

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
I-Type instructions
 Immediate-type
 3 operands:
 op: the opcode
 rs, rt: register operands
 imm: 16-bit two’s complement immediate

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits
I-Type Examples
Assembly Code Field Values
op rs rt imm

addi $s0, $s1, 5 8 17 16 5

addi $t0, $s3, -12 8 19 8 -12

lw $t2, 32($0) 35 0 10 32

sw $s1, 4($t1) 43 9 17 4
6 bits 5 bits 5 bits 16 bits

Machine Code
Note the differing order of
op rs rt imm
registers in the assembly and
001000 10001 10000 0000 0000 0000 0101 (0x22300005)
machine codes:
addi rt, rs, imm 001000 10011 01000 1111 1111 1111 0100 (0x2268FFF4)

lw rt, imm(rs) 100011 00000 01010 0000 0000 0010 0000 (0x8C0A0020)

sw rt, imm(rs) 101011 01001 10001 0000 0000 0000 0100 (0xAD310004)
6 bits 5 bits 5 bits 16 bits
J-Type instructions
 Jump-type
 26-bit address operand (addr)
 Used for jump instructions (j)

J-Type
op addr
6 bits 26 bits
Summary: Instruction Formats

R-Type
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-Type
op rs rt imm
6 bits 5 bits 5 bits 16 bits

J-Type
op addr
6 bits 26 bits
 MIPS Design from Comp411

We will not be implementing the textbook

version of MIPS in our labs.

Instead, we will implement the MIPS design

from Comp411, which has more features.

14
Design Approach
“Incremental Featurism”
 We will implement circuits for each type of instruction
individually, and merge them (using MUXes, etc).

Our Bag of Components:

Steps:
 1. 3-Operand ALU instrs Registers
 2. ALU w/immediate instrs
 2. Loads & Stores 0 1 Muxes
 3. Jumps & Branches
ALU & adders +
A B

 4. Exceptions (briefly) ALU

RA1 RA2
WA WD
Register A
Instruction
WE File A Data
D Memory Memory
WD (3-port) RD
R/W
RD1 RD2
Memories
Review: The MIPS ISA
OP
6 5 5 5 5 6 The MIPS
instruction set as
16
26

000000 rs rt rd shamt func seen from a

R-type: ALU with Register operands
Reg[rd]  Reg[rs] op Reg[rt]
Hardware
001XXX rs rt immediate Perspective
I-type: ALU with constant operand
Reg[rt]  Reg[rs] op SEXT(immediate)
Instruction
Instructionclasses
classes
10X011 rs rt immediate distinguished
distinguishedbybytypes:
types:
I-type: Load and Store 1) 3-operand
1) 3-operand ALUALU
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] 2)
2) ALUALUw/immediate
w/immediate
Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] 3) Loads/Stores
3) Loads/Stores
4)
4) Branches
10X011 rs rt immediate
5)
Branches
Jumps
5) Jumps
I-type: Branch Instructions
if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)

00001X 26-bit constant

J-type: jump
PC  (PC & 0xf0000000) | 4*(immediate)
Fetching Sequential Instructions

32

+
4
32 32
P Read
C
Address
32 Instruction
register
Instruction
Memory

We will talk about

branches and
jumps later.
Instruction Fetch/Decode
 Use a counter to FETCH
the next instruction:
 PROGRAM COUNTER (PC)
 use PC as memory address
PC 00
 add 4 to PC, load new value
A Instruction
32 Memory at end of cycle
+4 D
32
 fetch instruction from
32
INSTRUCTION memory
WORD  use some instruction fields
FIELDS directly (register numbers,
OP[31:26], FUNC[5:0] 16-bit constant)
Control Logic  decode rest of the instruction
 use bits <31:26> and <5:0>
CONTROL SIGNALS
to generate controls
3-Operand ALU Data Path
000000 rs rt rd 00000 100XXX

PC 00 R-type: ALU with Register operands

A Instruction Reg[rd]  Reg[rs] op Reg[rt]
Memory
D
+4

Rs: <25:21> Rt: <20:16>

RA1 RA2
Rd: <15:11> WA
Register WD
RD1
File RD2 WE WERF

32 32
Control Logic

A B
ALUFN ALU

ALUFN

WERF! WERF
32
Shift Instructions
000000 rs rt rd shamt 000XXX

PC 00 R-type: ALU with Register operands

A Instruction sll: Reg[rd]  Reg[rt] (shift) shamt
Memory
D
sllv: Reg[rd]  Reg[rt] (shift) Reg[rs]
+4
Rt: <20:16>
Rs: <25:21>

RA1 RA2
Rd: <15:11> WA
Register WD
RD1
File RD2 WE WERF

shamt:<10:6>

Control Logic 0 1 ASEL

A B
ALUFN ALU

ASEL! ALUFN

WERF
ASEL 32
ALU with Immediate
001XXX rs rt immediate

PC 00 I-type: ALU with constant operand

A Instruction
Memory
Reg[rt]  Reg[rs] op SEXT(immediate)
D
+4

Rs: <25:21> Rt: <20:16>

BSEL

Rd:<15:11>
0
RA1
Register RA2
WD
WA
WA
Rt:<20:16> 1
RD1
File RD2 WE WERF

imm: <15:0>
SEXT SEXT
shamt:<10:6> 1 0 BSEL

Control Logic 0 1 ASEL

SEXT
How do you
build SEXT?
A B
ALUFN ALU
BSEL! BSEL • 1  pad with sign
ALUFN • 0  pad with 0s

WERF
ASEL
Load Instruction
100011 rs rt immediate

I-type: Load
PC 00
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)]
A Instruction
Memory
D
+4

Rs: <25:21> Rt: <20:16>

BSEL

Rd:<15:11> RA1
Register RA2
0 WD
WA
WA
Rt:<20:16> 1 RD1
File RD2 WE WERF

Imm: <15:0>

SEXT SEXT
shamt:<10:6>

Control Logic 0 1 ASEL 1 0 BSEL

SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Adr RD
32
WERF
ASEL
32

0 1 2 WDSEL
Store Instruction
101011 rs rt immediate

PC 00
I-type: Store
A Instruction Mem[Reg[rs] + SEXT(immediate)]  Reg[rt]
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
BSEL

Rd:<15:11> RA1
Register RA2
0 WD
WA
WA
Rt:<20:16> 1 File
RD1 RD2 WE WERF
Imm: <15:0>

SEXT SEXT
shamt:<10:6>

Control Logic 0 1 ASEL 1 0 BSEL

32

A B
No WERF!
SEXT
BSEL ALUFN ALU WD R/W
Wr
WDSEL
ALUFN Data Memory
Wr Adr RD
WERF

ASEL

0 1 2 WDSEL
JMP Instructions
PC<31:28>:J<25:0>:00

00001X 26-bit constant

PCSEL 3 2 1 0
J-type:
PC 00 j: PC  (PC & 0xf0000000) | 4*(immediate)
A Instruction
Memory
jal: PC  (PC & 0xf0000000) | 4*(immediate);
+4 D Reg[31]  PC + 4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16> 0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

SEXT SEXT
shamt:<10:6>

Control Logic 0 1 ASEL 1 0 BSEL

PCSEL
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
BEQ/BNE Instructions
PC<31:28>:J<25:0>:00
BT
00010X rs rt immediate
PCSEL 3 2 1 0

R-type: Branch Instructions

PC 00
if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
A Instruction if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
That “x4” unit is Memory
trivial. I’ll just +4 D

wire the input

shifted over 2– Rs: <25:21>
Rt: <20:16>
bit positions. WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
SEXT SEXT
x4 shamt:<10:6>

Why add, another

adder? Couldn’t
Control Logic + 0 1 ASEL 1 0 BSEL

PCSEL
we reuse the one BT
WASEL
in the ALU? Nope, A B
SEXT
it needs to do a BSEL ALUFN ALU WD R/W Wr
subtraction. WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
Jump Indirect Instructions
PC<31:28>:J<25:0>:00

rs rt rd
JT BT
000000 00000 00100X
PCSEL 3 2 1 0

R-type: Jump Indirect, Jump and Link Indirect

jr: PC  Reg[rs]
PC 00

Instruction
Memory jalr: PC  Reg[rs], Reg[rd]  PC + 4
A

D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + 0 1 ASEL 1 0 BSEL

PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
Comparisons
PC<31:28>:J<25:0>:00 00101X rs rt immediate
JT BT
I-type: set on less than & set on less than unsigned immediate
PCSEL 3 2 1 0
slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0
PC 00 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0
A Instruction
Memory
D
NOTE: Sign-extension
+4
done for both! WHY??
Rs: <25:21>
Rt: <20:16> But ALUFN is unsigned
J:<25:0>
WASEL comparison (LTU) for sltiu.
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>
JT SEXT SEXT
Z
x4 shamt:<10:6>

Control Logic + 0 1 ASEL 1 0 BSEL

PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
More comparisons
PC<31:28>:J<25:0>:00 000000 rs rt rd 00000 10101X
JT BT
R-type: set on less than & set on less than unsigned
PCSEL 3 2 1 0
slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0
PC 00 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0
A Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + 0 1 ASEL 1 0 BSEL

PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
LUI
PC<31:28>:J<25:0>:00
JT BT 001111 00000 rt immediate

PCSEL 3 2 1 0 I-type: Load upper immediate

lui: Reg[rt]  Immediate << 16
PC 00

A Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + “16”

ASEL BSEL
0 1 2 1 0
PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL

PC+4
32
0 1 2 WDSEL
All put together…
PC<31:28>:J<25:0>:00
JT BT

PCSEL 3 2 1 0

PC 00

A Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + “16”

ASEL BSEL
0 1 2 1 0
PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL

PC+4
32
0 1 2 WDSEL
Reset, Interrupts, and Exceptions
 Upon reset/reboot:
 Need to set PC to where boot code resides in memory
 Interrupts/Exceptions:
 any event that causes interruption in program flow
 FAULTS: e.g., nonexistent opcode, divide-by-zero
 TRAPS & system calls: e.g., read-a-character
 I/O events: e.g., key pressed
 How to handle?
 interrupt current running program
 invoke exception handler
 return to program to continue execution
 Registers $k0, $k1 ($26, $27)
 reserved for operating system (kernel), interrupt handlers
 any others used must be saved/restored
Exceptions
0x80000000
Reset: PC  0x80000000
PC<31:28>:J<25:0>:00
0x80000040
0x80000080 JT BT

PCSEL 6 5 4 3 2 1 0
Bad Opcode: Reg[27]  PC+4; PC  0x80000040
IRQ: Reg[27]  PC+4; PC  0x80000080
PC 00

A Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31
27
2
3 RD1
File RD2 WE WERF

Imm: <15:0>
RESET
JT SEXT SEXT
IRQ Z
x4 shamt:<10:6>

Control Logic + “16”

ASEL BSEL
0 1 2 1 0
PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL

PC+4
32
0 1 2 WDSEL
 Our Lab version: three changes

1. No support for exceptions

2. Supports Reset: PC starts over at 0x0040_0000
 address chosen for compatibility with MARS
assembler
3. Supports Enable: Freezes when Enable = 0
 will allow us to “single-step” through execution
 debugging aid
33
Support for Reset
 “Reset” input: starts PC over at 0x0040_0000
 address chosen for compatibility with MARS assembler
PC<31:28>:J<25:0>:00
JT B
T On Reset: PC  0x0040_0000
PCSEL 3 2 1 0

PC 00

A Instruction
Memory
RESET D
+4
Rt: <20:16>
Rs:
J:<25:0>
WASEL <25:21>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + “16”

0 1 2 ASEL 1 0 BSEL
PCSEL
B
WASEL T
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
Support for Enable
 “Enable” input: Enable = 0 disables the processor
 disables writes to: PC, register file and data memory
PC<31:28>:J<25:0>:00
JT B
T On Reset: PC  0x0040_0000
PCSEL 3 2 1 0

PC 00

A Instruction
ENABLE Memory
RESET
Writes disabled
D
+4

Rs:
Rt: <20:16> by controller
J:<25:0>
WASEL <25:21>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2
WD
WA
WA
31 2
RD1
File RD2 WE WERF

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + “16”

0 1 2 ASEL 1 0 BSEL
PCSEL
B
WASEL T
SEXT A B
BSEL ALUFN ALU WD R/W Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL
PC+4
32
0 1 2 WDSEL
MIPS: Our Final Version
PC<31:28>:J<25:0>:00
This is a complete 32-bit processor.
JT BT Although designed in “one” class lecture,
PCSEL 3 2 1 0
it executes the majority of the
PC 00 MIPS R2000 instruction set.
A Instruction
ENABLE Memory
RESET
D
+4
Rt: <20:16>
Executes one
WASEL
Rs: <25:21>
instruction
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
RA1
Register RA2 per clock
WA
WA WD
31 2 File WERF
RD1 RD2 WE

Imm: <15:0>

Z
JT SEXT SEXT
x4 shamt:<10:6>

Control Logic + “16”

0 1 2 ASEL 1 0 BSEL
PCSEL
BT
WASEL
SEXT A B
BSEL ALUFN ALU WD R/W
Wr
WDSEL
ALUFN Data Memory
Wr Z Adr RD
WERF
ASEL

PC+4
32
0 1 2 WDSEL
Our MIPS: Top-level hierarchy
PC<31:28>:J<25:0>:00
JT BT

PCSEL 3 2 1 0
newPC pcPlus4

PC 00

ENABLE A Instruction MIPS CPU

pc pc[31:0] Memory
RESET D Datapath
+4
instr

Rt: instr<20:16>
Rs: instr<25:21>

reg_writeaddr
WASEL
J: instr<25:0>
Rd: instr<15:11> 0
Rt: instr<20:16> 1
RA1
Register RA2
WD
reg_writedata
WA
WA
31 2
RD1
File RD2 WE WERF
ReadData1 ReadData2
Imm: instr<15:0>
ENABLE Z op: instr<31:26>
func: instr<5:0> JT SEXT SEXT
signImm
<<2 shamt: instr<10:6>

Control Logic + “16”

ASEL BSEL
0 1 2 1 0 mem_writedata
PCSEL
BT aluA aluB
WASEL
SEXT A B
mem_wr
BSEL ALUFN ALU WD R/W
Wr
WDSEL
ALUFN Data Memory
mem_addr
Wr Z Adr RD
WERF
alu_result
ASEL mem_readdata

pcPlus4 (PC+4)
32
0 1 2 WDSEL
 Make design modular
 Follow hierachy specified
 Small amounts of logic can be
“inlined” (instead of separate
module)
 e.g.: muxes, sign extension,
adders, shift-by-2

38
Summary
 We learned about a complete MIPS CPU
 NOTE: Many details in textbook are different…
 … from what you will implement in the lab
 our lab MIPS has more features