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Transistors and All That : COMP541

This document provides an overview of transistors and CMOS logic gates. It describes how transistors function as switches and how doping silicon with impurities creates n-type and p-type semiconductors. MOS transistors are explained as having three terminals - gate, source, and drain. CMOS logic uses complementary nMOS and pMOS transistors to implement basic logic functions like inverters, NAND, and NOR gates. Complex CMOS gates can perform more advanced logic operations by combining multiple transistors in specific configurations.

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0% found this document useful (0 votes)
94 views29 pages

Transistors and All That : COMP541

This document provides an overview of transistors and CMOS logic gates. It describes how transistors function as switches and how doping silicon with impurities creates n-type and p-type semiconductors. MOS transistors are explained as having three terminals - gate, source, and drain. CMOS logic uses complementary nMOS and pMOS transistors to implement basic logic functions like inverters, NAND, and NOR gates. Complex CMOS gates can perform more advanced logic operations by combining multiple transistors in specific configurations.

Uploaded by

danya314
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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COMP541

Transistors and all that…


a brief overview

Montek Singh

Feb {7, 12}, 2018

1
Transistors as switches
 At an abstract level, transistors are merely switches
 3-ported voltage-controlled switch
 n-type: conduct when control input is 1
 p-type: conduct when control input is 0

g=0 g=1

d d d
nMOS g OFF
ON
s s s

s s s

pMOS g OFF
ON
d d d

2
Silicon as a semiconductor
 Transistors are built from silicon
 Pure Si itself does not conduct well
 Impurities are added to make it conducting
 As provides free electrons  n-type
 B provides free “holes”  p-type

Figure 1.26 Silicon lattice and dopant atoms


MOS Transistors
 MOS = Metal-oxide semiconductor
 3 terminals
 gate: the voltage here controls whether current flows
 source and drain: are what the current flows between
 structurally, source and drain are the same

Figure 1.29 nMOS and pMOS transistors


nMOS Transistors
 Gate = 0  Gate = 1
 OFF = disconnect  ON= connect
 no current flows  current can flow between
between source & drain source & drain
 positive gate voltage
draws in electrons to
form a channel

Figure 1.30 nMOS transistor operation


nMOS and pMOS Transistors
 pMOS: Just the opposite
 Gate = 1  disconnect
 Gate = 0  connect

 Summary:
g=0 g=1

d d d
nMOS g OFF
ON
s s s

s s s

pMOS g OFF
ON
d d d
6
CMOS Topologies
 There is actually more to it than connect/disconnect
 nMOS: pass good 0’s, but bad 1’s
 so connect source to GND
 pMOS: pass good 1’s, but bad 0’s
 so connect source to VDD pMOS
pull-up
 Typically use them in network
inputs
complementary fashion: output
 nMOS network at bottom
nMOS
 pulls output value down to 0 pull-down
network
 pMOS network at top
 pulls output value up to 1
 only one of the two networks must conduct at a time!
 or output is undefined (or smoke may be produced!)
 if neither network conducts  output will be floating
7
CMOS Gate Recipe
 Use complementary networks of p- and n-transistors
 called CMOS (“complementary metal-oxide semiconductor”)
 at any time: either “pullup” active, or “pulldown” active
 never both!

VDD Use p-type


here

pMOS
pull-up pullup: make this connection
network when some combination of inputs
inputs is near 0 so that output = VDD
output

nMOS
pull-down
pulldown: make this connection
network when some combination of inputs
is near VDD so that output = 0 (Gnd)
Use n-type
here
Gnd
CMOS Inverter
“0” “1”

Vout
Valid “1”

Vin Vout
Invalid

“1” “0”

Valid “0”
Vin

Only a narrow
range of input
A Y voltages result in
“invalid” output
inverter values. (This
diagram is greatly
exaggerated)
CMOS Complements
A A

conducts when A is high conducts when A is low

A
Series N connections: A B
B Parallel P connections:

conducts when A is high conducts when A is low


and B is high: A.B or B is low: A+B = A.B

A
A B
B
Parallel N connections: Series P connections:

conducts when A is high conducts when A is low


or B is high: A+B and B is low: A.B = A+B
Inverter

NOT VDD
A Y
P1
Y=A A Y
N1
A Y
0 1
GND
1 0

A P1 N1 Y
0 ON OFF 1
1 OFF ON 0

11
NAND
NAND
A
Y
B P2 P1
Y
Y = AB
A N1
A B Y
0 0 1 B N2
0 1 1
1 0 1
1 1 0

A B P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
12
3-Input NAND
NOR
3-input NOR

A
B
C
Y

15
2-input AND Gate?

A
Y
B

16
A More Complex CMOS Gate
 Design a single gate that computes Y =(A + B)×C

 Step 1. Determine pull-down network that C


sets output to ‘0’
A B
 (A OR B) AND C  Y=0

 Step 2. Determine pull-up network by walking


A
through pulldown hierarchy, and C
B
 replacing n-transistors with p-transistors
 series composition with parallel composition
 parallel composition with series composition A
C
B
Y
C
 Step 3. Combine the pull-up and pull-down
networks together A B
A More Complex CMOS Gate
 Single gate that computes Y =(A + B)×C
 called “complex gate” because it is not
one of the basic gates (NAND, NOR,
NOT, etc.)
A
C

B
 this one is actually called
Y
OR-AND-INVERT (OAI)
C

 symbol: A
B
One More Exercise
 Lets construct a gate to compute:
 F = A+BC = NOT(OR(A,AND(B,C)))
Vdd
A

 Step 1: Draw the pull-down network B C


 Step 2: The complementary pull-up
network F
A B

 this one is called AND-OR-INVERT C


(AOI)
One More Exercise
 Lets construct a gate to compute:
 F = A+BC = NOT(OR(A,AND(B,C)))

Vdd
 Step 1: Draw the pull-down network A
 Step 2: The complementary pull-up
B C
network F
 Step 3: Combine and Verify A B C F A B
0 0 0 1
C
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Transmission Gates
 Transmission gate is a switch:
En
 nMOS pass 1’s poorly
 pMOS pass 0’s poorly
 Transmission gate is a better switch A B
 passes both 0 and 1 well
 When EN = 1, the switch is ON:
 A is connected to B
 When EN = 0, the switch is OFF: En
 A is not connected to B
En

 Symbol:
A B

En
Transmission Gate
 IMPORTANT: Transmission
gates are not drivers
 will NOT remove input noise to
En
produce clean(er) output
 simply connect A and B together
 current could even flow backward! A B
 use very carefully!
 immediately follow it up with a
normal CMOS gate

En
Logic using Transmission Gates
 Typically combine two (or more) transmission gates
 Together form an actual logic gate whose output is always
driven 0 or 1
 Exactly one transmission gate drives the output;
all remaining transmission gates float their outputs
 Example: XOR
 when C = 0, TG0 conducts
F = A
 when C = 1, TG1 conducts
TG0
 F = A’
 therefore:
 F = A xor C
TG1

23
Tristate buffer and tristate inverter
 When enabled: sends input to output
 When disabled: output is floating (‘Z’)
 Implementation: E

 Tristate buffer using only a pass gate A Y


 If on: output  input EN
 If off: output is floating E A Y
0 0 Z
A Y 0 1 Z
1 0 0
EN 1 1 1

 Tristate inverter
 Top half and bottom half are not fully
complementary
 Either both conduct: output  NOT(input)
– will act as a driver!
 Or both off: output is floating

24
Power and Energy Consumption

25
Power Consumption
 Power = Energy consumed per unit time
 Dynamic power consumption
 Static power consumption
Dynamic Power Consumption
 Energy consumed due to switching activity:
 All wires and transistor gates have capacitance
 Energy required to charge a capacitance, C, to VDD is CVDD2
 Circuit running at frequency f: transistors switch (from 1 to 0
or vice versa) at that frequency
 Capacitor is charged f/2 times per second
 assume 50% chance switching from 0 to 1
– additional energy drawn from battery  CVDD2
 assume 50% chance switching from 1 to 0
– no additional energy taken from battery  stored energy is discharged

Pdynamic = ½CVDD2f
C is the total capacitance of circuit (“capacitive load”)
VDD is the supply voltage
f is the switching frequency
Static Power Consumption
 Power consumed when no gates are switching
 Caused by the quiescent supply current, IDD (also called the
leakage current)
Pstatic or Pleakage = IDDVDD

VDD is the supply voltage


IDD is the leakage current
Power Consumption Example
 Estimate the power consumption of a wireless
handheld computer
 VDD = 1.2 V
 C = 20 nF
 f = 1 GHz
 IDD = 20 mA

P = ½CVDD2f + IDDVDD
= ½(20 nF)(1.2 V)2(1 GHz) + (20 mA)(1.2 V)
= 14.4 W + 24 mW
= 14.424 W

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