Digital Logic Design: Multiplexer & De-Multiplexer
Digital Logic Design: Multiplexer & De-Multiplexer
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Multiplexer or Mux or Data Selector
• In the old days, several machines could share an I/O device with a Switch.
• The Switch allows one computer’s output to go to the printer’s input.
Q = S’ D0 + S D1
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4-input multiplexer
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Timing Diagram
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6
7
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8-to- 1 Mux using ONLY 4-to-1 Mux
D0 0
4X1
D0
8X1
Y1
D0
D3 3
0
4X1
Y S1 S0
Y3
D7
D3 3
D4 0
4X1
S1 S0
Y2
S2 S1 S0
D7 3
S1 S0
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Implementing functions with multiplexers
• Muxes can be used to implement arbitrary functions.
• One way to implement a function of n variables is to use an 2n-to-1 mux:
• For example, let’s look at f(x,y,z) = (1,2,6,7).
x y z f
0 0 0 0 D0
0 0 1 1 D1
0 1 0 1 D2
0 1 1 0 D3
1 0 0 0 D4
1 0 1 0 D5
1 1 0 1 D6
1 1 1 1 D7
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MULTIPLEXER
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Procedure:
1) Implement the truth table,
2) Write the SOP expression in the decimal format, F(A,B,C)= Σ (1, 3, 5, 6)
3) If the Boolean function has n+1 Variables, then connect n of these variables to
the select lines of a MUX maintain the order.
4) Based on the select lines, find the total number of input lines for the MUX. The
remaining variable will be used for the inputs of the MUX.
2 0 1 0 0 1
3 0 1 1 1 4X1
2 F
4 1 0 0 0
3
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0 B C
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• Consider now the single variable A. It can either be 0 or 1.
• From the truth table, find the minterms for which A is 0. The minterms are 0, 1, 2 & 3.
• From the truth table, find the minterms for which A is 1. The minterms are 4, 5, 6 & 7.
Minterms A B C F
0 0 0 0 0
1 0 0 1 1
I0 I1 I2 I3
2 0 1 0 0
A’ 0 1 2 3
3 0 1 1 1
A 4 5 6 7
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
• List the inputs of the MUX and under them list all the minterms in two rows.
• The first row lists all those minterms where A is 0, and the second row all the
minterms with A is 1.
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• Circle all the minterms of the function and inspect each column separately.
F(A,B,C)= Σ (1, 3, 5, 6)
I0 I1 I2 I3
A’ 0 1 2 3
A 4 5 6 7
0 1 A
A’
• If the two minterms in a column are not circled, apply 0 to the corresponding MUX input.
• If the two minterms are circled, apply 1 to the corresponding MUX input.
• If the bottom minterm is circled and the top is not circled, apply A to the corresponding
MUX input.
• If the top minterm is circled and the bottom is not circled, apply A’ to the corresponding
MUX input.
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F(A,B,C)= Σ (1, 3, 5, 6)
Minterms A B C F I0 I1 I2 I3
0 0 0 0 0
A’ 0 1 2 3
A 4 5 6 7
1 0 0 1 1
0 1 A
2 0 1 0 0
A’
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1 0 0
6 1 1 0 1 1 1
4X1
7 1 1 1 0 A 2 F
A’ 3
B C
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Example:
Implement the following function with only one 8-to-1 multiplexer:
I0 I1 I2 I3 I4 I5 I6 I7
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 A’ A’ 0 0 A
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Example:
Implement the following function using 4x1
MUX:
F(A,B,C)= Σ (2, 3, 4, 6)
Minterms A B C F I0 I1 I2 I3
A’ 0 1 2 3
0 0 0 0 0 A 4 5 6 7
1 0 0 1 0 A 0 1 A’
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
A 0
5 1 0 1 0
0 1
6 1 1 0 1 4X1
2 Y
7 1 1 1 0 1
A’ 3
B C
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Example:
F(A,B,C)= Σ (2, 3, 4, 6)
I0 I1 I2 I3
B 0
B’ 0 1 4 5
B 1
B 2 3 6 7 4X1
Minterms A B C F 1 2 Y
B B 1 0
0 3
0 0 0 0 0
1 0 0 1 0 A C
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
5 1 0 1 0
I0 I1 I2 I3
6 1 1 0 1 0 0
C’ 0 2 4 6
7 1 1 1 0 1 1
C 1 3 5 7 4X1
2 Y
C’
0 1 C’ C’
C’ 3
A B 18
Example:
A’ 0
F(A,B,C,D)= Σ (0,2,3,6,7,9,12,13,15) A 1
2
A’
I0 I1 I2 I3 I4 I5 I6 I7
A’ 0 1 2 3 4 5 6 7 A’ 3
8X1
A 4 Y
A 8 9 10 11 12 13 14 15
A’ A A’ A’ A A A’ 1 A 5
A’ 6
1 7
Example: AND gate
F(A,B)= AB B C D
A B F
I0 I1
0 0 0 A’ 0 1 0 0
0 1 0 A 2 3 2X1
A 1 F
1 0 0 0 A
1 1 1
B 19
Example:
F(A,B,C) = AB+BC Minterm A B C F
0 0 0 0 0
F = AB+BC 1 0 0 1 0
2 0 1 0 0
= AB(C+C’)+(A+A’)BC 3 0 1 1 1
= ABC+ABC’+ABC+A’BC 4 1 0 0 0
= ABC+ABC’ +A’BC 5 1 0 1 0
7 6 3 6 1 1 0 1
7 1 1 1 1
0 0
I0 I1 I2 I3 0 1
A’ 0 1 2 3 4X1
2 Y
A
A 4 5 6 7
1 3
0 0 A 1
B C
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Summary
• A 2n-to-1 multiplexer routes one of 2n input lines to a single output line.
• Just like decoders,
– Muxes are common enough to be supplied as stand-alone devices for use in
modular designs.
– Muxes can implement arbitrary functions.
• We saw some variations of the standard multiplexer:
– Smaller muxes can be combined to produce larger ones.
– We can add active-low or active-high enable inputs.
• As always, we use truth tables and Boolean algebra to analyze things.
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Demultiplexers
2-line-to 4-line
demux
D0=S1’S0’Din
D1=S1’S0Din
D2=S1S0’Din
D3=S1S0Din
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Timing Diagram
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Cascading DEMUX
Designing a 1x11 DEMUX using 1x2 DEMUX
0
1
2
3
4
5
6
7
1X16
I
8
9
10
11
12
13
14
15
S3 S2 S1 S0
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Reference:
Mixed contents from books by Floyd; Mano; Vahid
And Howard.
Acknowledgement:
Nafiz Ahmed
Chisty
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Thank
s 26