Chapter II

Programming the Microprocessor, Memory,

and IO Organization

 
Programming the Microprocessor 8086/8088
• 8086 CPU can access up to 1 MB of Random Access Memory (RAM),
it is limited by segment/offset construction.
• Segment registers (CS, SS, ES, DS) can hold maximum value
of 0FFFFh.
• The offset registers (IP, BX, SI, DI, BP, SP) can also hold maximum
value of 0FFFFh.
• Therefore, the largest logical memory location that we can access
is FFFF:FFFF 
or physical address: 0FFFFh * 10h + 0FFFFh = 10FFEFh = 65535 *
16 + 65535 = 1,114,095 bytes 
• Modern processors have a larger registers so they have much larger
memory area that can be accessed, but the idea is still the same. 
Physical address of
Short Description
memory area in HEX
Interrupt vectors. Emulator loads "INT_VECT" file at the
00000 – 00400
physical address 00000h.
00400 – 00500 System information area.
A free memory area. A block of 654,080 bytes. Here you can
00500 - A0000
load your programs.
Video memory for VGA, Monochrome, and other adapters.
A0000 - B1000
Not used by emulator!
B1000 - B8000 Reserved. Not used by emulator!
32 KB video memory for Color Graphics Adapter (CGA).
B8000 - C0000 Emulator uses this memory area to keep 8 pages (4096 bytes)
of video memory.
C0000 - F4000 Reserved.
ROM BIOS and extensions. Emulator loads "BIOS_ROM" file
F4000 - 10FFEF at the physical address 0F4000h. Interrupt table points to this
memory area to get emulation of interrupt functions.
Programming
A Program to display the given string and print it out using DOS function
interrupt INT 21h is given below.
#make_COM# ; COM file is loaded at 100h
ORG 100H
MOV AX, CS ; set data segment:
MOV DS, AX
MOV ES, AX
MOV DX, offset MSG
ADD DX, 2 ;to skip first 2 bytes
MOV AH, 09H ;INT 21H / AH=09H - output of a string at DS:DX
INT 21H
MOV AH, 4CH ;INT 21H / AH=4CH - exit to operating system
INT 21H
MSG DB 30, 30, "GOOD MORNING",'$' ; first byte is buffer size,
second byte is actual number of characters in the string
END
A program may use directives, macros, procedures, variables, and constants. Macros is
described here.
Macros
Macros are just like procedures, but not really. After compilation all macros are replaced
with real instructions. The Macro definition is:
name MACRO [parameters,...]
<instructions>
ENDM
Unlike procedures, macros should be defined above the code that uses it. For example the
following file contains several macros to make coding easier.
MyMacro MACRO p1, p2, p3
MOV AX, p1
The above code is expanded into:
MOV BX, p2 MOV AX, 0001h
MOV CX, p3 MOV BX,0002h
ENDM MOV CX,0003h
ORG 100h MOV AX,0004h
MOV BX,0005h
MyMacro 1, 2, 3 MOV CX, DX
MyMacro 4, 5, DX
RET
 Hardware Specification : Figure illustrates the pin-outs of the 8086, aged
 
 
in 40-pin dual in-line packages (DIPs). is a 16-bit microprocessor with a 16-
bit data bus AD0–AD15.
Pin Connections
AD15–AD0 These are the time multiplexed memory I/O address and data lines.

AD7–AD0 : When ALE= logic 1, the lines carry the rightmost 8 bits of the
memory address or I/O port number.
• When ALE= logic 0, the lines carry the rightmost 8 bits of data.
•These pins are at their high-impedance state during a hold acknowledge.
AD15–AD8: When ALE= logic 1, the lines carry the address bits A15–A8.
•When ALE= logic 0, the lines carry the data bits D15–D8.
•These pins enter a high-impedance state when a hold acknowledge occurs. 
A19/S6–A16/S3: The address/status bus bits are multiplexed to provide
address signals
•A19–A16 and also status bits S6–S3.
•These pins also attain a high-impedance state during the hold acknowledge.
Status bit S6 =logic 0, always;
bit S5 =IF flag bit, and
S4 and S3 show which segment is accessed during the
current bus cycle, as shown in table below.
S4 S3 Function
0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data segment
These two status bits could be used to address four separate 1M byte
memory banks by decoding them as A21 and A20.
 The pin
configuration of the
8086 in minimum and
maximum modes
RD Whenever the read signal is a logic 0, the data bus
will carry data from the memory or I/O devices
connected to the system.
This pin floats to its high-impedance state during a
hold acknowledge.
NMI The non-maskable interrupt input is similar to INTR except that the NMI
interrupt does not check to see whether the IF flag bit is a logic 1. If NMI is
activated, this interrupt input uses interrupt vector 2.
RESET The reset input causes the microprocessor to reset itself if this pin is held high
for a minimum of four clocking periods. Whenever the 8086 or 8088 is reset, it
begins executing instructions at memory location FFFF0H and disables future
interrupts by clearing the IF flag bit.
CLK The clock pin provides the basic timing signal to the microprocessor. The clock
signal must have a duty cycle of 33 % (high for one third of the clocking period and
low for two thirds) to provide proper internal timing for the 8086/8088.
 VCC This power supply input provides a +5.0 V, ±10 % signal to the microprocessor.

GND The ground connection is the return for the power supply.
Note that it has two pins labeled GND—both must be connected to ground for
proper operation.
Minimum Mode
Queue status bits:

QS1 QS0 Function

0 0 Queue is idle
0 1 First byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode
Memory Interface
Fig 1 and 2 below show the 74LS138 3-to-8 line decoder and its function table.
 Fig 3 below is the circuit that uses eight 2764 EPROMs for a
64K  8 chips of memory in an 8086 microprocessor-based
system. The addresses selected in this circuit are F0000H–
FFFFFH.
Notice that the outputs of the decoder, illustrated in Fig2 are connected to
eight different 2764 EPROM memory devices. Here, the decoder selects eight
8Kbyte blocks of memory for a total memory capacity of 64K bytes. Table
below shows how the address range of the entire decoder is determined. This is
a 64K-byte span of the memory.
1111 XXXX XXXX XXXX XXXX
or
1111 0000 0000 0000 0000 = FOOOOH
to
1111 1111 1111 1111 1111 = FFFFFH
The Basic Input Interface: Three-state buffers are used to construct the 8-bit input port
depicted in Figure
The Basic Output Interface: The basic output interface receives data
from the microprocessor and usually must hold it in latches or flip-
flops,( like the buffers) for some external device.
Below Fig. shows how eight simple light-emitting diodes (LEDs)
connect to the microprocessor through a set of eight data latches.
The latch stores the ASCII data from the data bus because the data
are only present on the data bus for less than 1.0 μs. Without a
latch, the viewer would never see the LEDs illuminate.
 
When the OUT instruction executes, the data from AL, AX, or EAX
are transferred to the D inputs of 74ALS374 octal latch via the data
bus.
The Q outputs of the latch are attached to the LEDs.
When a Q output becomes logic 0, the LED lights.
The basic output interface connected to a set of LED displays.
 Bus Interface

Fig. illustrates the placement of all buses in the Pentium 4

system. The popular buses are

(i) The ISA (industry standard architecture) bus

(ii)The PCI (peripheral component interconnect) and PCI Express

buses,

(iii)The USB (universal serial bus), and

(iv)The AGP (accelerated graphics port).

Structure of a modern computer, illustrating all the buses.