Embedded Systems

Engr. Rashid Farid Chishti

[email protected]

Chapter 17: SPI PROTOCOL AND

MAX7221 DISPLAY INTERFACING

International Islamic University H-10, Islamabad, Pakistan

http://www.iiu.edu.pk
 SPI BUS Protocol
 The SPI (serial peripheral interface) is a bus
interface connection incorporated into many
devices such as ADC, DAC, and EEPROM.
 The SPI bus was originally started by Motorola
Corp. (now Freescale), but in recent years has
become a widely used standard adapted by many
semiconductor chip companies.
 SPI devices use only 2 pins for data transfer,
called SDI (Din) and SDO (Dout).
 This reduction of data pins reduces the package
size and power consumption, making them ideal
for in which space is a major concern.
 The SPI bus has the SCLK (shift clock) pin to
synchronize the data transfer between two chips.
 The last pin of the SPI bus is CE (chip enable),
which is used to initiate and terminate the data
transfer.
 SPI BUS Protocol
 These 4 pins, SDI, SDO, SCLK, and CE, make the
SPI a 4-wire interface.
 The SDI, SDO, SCLK, and CE signals are
alternatively named as MOSI, MISO, SCK, and SS.
 SPI BUS Protocol
 There is also a widely used standard called a 3-
wire interface bus. In a 3-wire interface bus,
we have SCLK and CE, and only a single pin for
data transfer.
 The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied
together.
 But there are some major differences between the
SPI and 3-wire devices in the data transfer
protocol.
 For that reason, a device must support the 3-
wire protocol internally in order to be used as
a 3-wire device.
 Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols.
 HOW SPI WORKS?
 SPI consists of two shift registers, one in the
master and the other in the slave side. Also,
there is a clock generator in the master side
that generates the clock for the shift
registers.
 HOW SPI WORKS?
 The serial-out pin of the master shift register
is connected to the serial-in pin of the slave
shift register by MOSI (Master Out Slave In).
 The serial-in pin of the master shift register
is connected to the serial-out pin of the slave
shift register by MISO (Master In Slave Out).
 The master clock generator provides clock to the
shift registers in both the master and slave.
 The clock input of the shift registers can be
falling- or rising-edge triggered.
 Shift registers are 8 bits long. So after 8
clock pulses, the contents of the two shift
registers are interchanged.
 When the master wants to send a byte of data, it
places the byte in its shift register and
generates 8 clock pulses.
 HOW SPI WORKS?
 After 8 clock pulses the byte is transmitted to
the other shift register.
 When the master wants to receive a byte of data,
the slave side should place the byte in its
shift register, and after 8 clock pulses the
data will be received by the master shift
register.
 It must be noted that SPI is full duplex,
meaning that it sends and receives data at the
same time.
 SPI read and write
 We use the microcontroller as the master while
the SPI device acts as a slave. So the µc
generates the SCLK, which is fed to the SCLK pin
of the SPI device.
 The SPI protocol uses SCLK to synchronize the
transfer of information one bit at a time, where
the most-significant bit (MSB) goes in first.
 During the transfer, the CE must stay HIGH.
 The information (address and data) is transferr-
ed between the microcontroller and the SPI
device in groups of 8 bits, where the address
byte is followed immediately by the data byte.
 To distinguish between the read and write
operations, the D7 bit of the address byte is
always 1 for write, while for the read, the D7
bit is LOW.
 Clock Polarity and Phase in SPI device
 In SPI communication, the master and slave(s)
must agree on the clock polarity and phase with
respect to the data.
 Freescale names these two options as CPOL (clock
polarity) and CPHA (clock phase), respectively,
and most companies like Atmel have adopted that
convention.
 At CPOL = 0 the base value of the clock is zero,
while at CPOL = 1 the base value of the clock is
one. CPHA = 0 means sample on the leading
(first) clock edge, while CPHA = 1 means sample
on the trailing (second) clock.
 If the base value of the clock is zero, the
leading (first) clock edge, is the rising edge
but if the base value of the clock is one, the
leading (first) clock edge is falling edge.
 Clock Polarity and Phase in SPI device
The base value of clock is Zero

The base value of clock is One

Sample on First Clock Edge

Sample on Second Clock Edge

 Steps for writing data to an SPI device
 In accessing SPI devices, we have two modes of
operation: single-byte and multibyte.
Single-byte write:
1. Make CE = 0 to begin writing.
2. The 8-bit address is shifted in, one bit at a
time, with each edge of SCLK. Notice that A7 = 1
for the write operation, and the A7 bit goes in
first.
 Steps for writing data to an SPI device

3. After all 8 bits of the address are sent in, the

SPI device expects to receive the data belonging
to that address location immediately.
4. The 8-bit data is shifted in one bit at a time,
with each edge of the SCLK.
5. Make CE = 1 to indicate the end of the write
cycle
Steps for writing data to an SPI device
Multi-byte burst write:
 In burst mode, we provide the address of the
first location, followed by the data for that
location. From then on, while CE = 0,
consecutive bytes are written to consecutive
memory locations.
 In this mode, the SPI device internally
increments the address location as long as CE is
LOW.
 The following steps are used to send (write)
multiple bytes of data in burst mode for SPI
devices as shown in Figure 17-5:
1. Make CE = 0 to begin writing.
2. The 8-bit address of the first location is
provided and shifted in, one bit at a time, with
each edge of SCLK. Notice that A7 = 1 for the
write operation and the A7 bit goes in first.
 Steps for writing data to an SPI device

3. The 8-bit data for the first location is

provided and shifted in, one bit at a time, with
each edge of the SCLK.
4. From then on, we simply provide con secutive
bytes of data to be placed in consecutive memory
locations. In the process, CE must stay low to
indicate that this is a burst mode multibyte
write operation.
5. Make CE = 1 to end writing.
Steps for reading data from an SPI device
Single-byte read
1. Make CE = 0 to begin reading.
2. The 8-bit address is shifted in one bit at a
time, with each edge of SCLK. Notice that A7 = 0
for the read operation, and the A7 bit goes in
first.
3. After all 8 bits of the address are sent in, the
SPI device sends out data belonging to that
location.
4. The 8-bit data is shifted out one bit at a time,
with each edge of the SCLK.
5. Make CE = 1 to indicate the end of the read
cycle
 Steps for reading data from an SPI device
4. The 8-bit data is shifted out one bit at a time,
with each edge of the SCLK.
5. Make CE = 1 to indicate the end of the read
cycle.
Multi-byte burst read
 In burst mode, we provide the address of the
first location only. From then on, while CE = 0,
consecutive bytes are brought out from
consecutive memory locations.
 In this mode, the SPI device internally
increments the address location as long as CE is
LOW.
 The following steps are used to get (read)
multiple bytes of data in burst mode for SPI
devices
 Steps for reading data from an SPI device
1. Make CE = 0 to begin reading.
2. The 8-bit address of the first location is
provided and shifted in, one bit at a time, with
each edge of SCLK. Notice that A7 = 0 for the
read operation, and the A7 bit goes in first.
3. The 8-bit data for the first location is shifted
out, one bit at a time, with each edge of the
SCLK. From then on, we simply keep getting
consecutive bytes of data belonging to
consecutive memory locations. In the process, CE
must stay LOW to indicate that this is a burst
mode multibyte read operation.
4. Make CE = 1 to end reading.
 Steps for reading data from an SPI device
consecutive bytes of data belonging to
consecutive memory locations. In the process, CE
must stay LOW to indicate that this is a burst
mode multibyte read operation.
4. Make CE = 1 to end reading.
SPI Programming in AVR
In AVR three registers are associated with SPI.
They are SPSR (SPI Status Register), SPCR (SPI
Control Register), and SPDR (SPI Data Register)
SPI Programming in AVR
SPI Programming in AVR
In Table 17-2 you see how SPI2X, SPR1, and SPRO
are combined to make different clock frequencies
for master. As you see in Table 17-2, by setting
SPI2X to one, the SCK frequency is doubled.
SPI Programming in AVR
SPDR (The SPI Data Register)
 The SPI Data Register is a read/write register.
To write into SPI shift register, data must be
written to SPDR. To read from the SPI shift
register, you should read from SPDR. Writing to
the SPDR register initiates data transmission.
 Notice that you cannot write to SPDR before the
last byte is transmitted completely, otherwise a
collision will happen. You can read the received
data before another byte of data is received
completely.
SPI Programming in AVR
SS pin in AVR
 The Slave Select (SS) pin of the SPI bus is used
to initiate and terminate the data transfer. In
AVR, there are some points regarding this pin
that you should pay attention to.
 When you are in master mode, you can choose to
make this pin either input or output. If you
make it output, the SPI circuit of AVR will not
control the SS pin and you can make it one or
zero by software.
 When you make the SS pin an input, it will
control the function of SPI. In this case you
should externally make SS pin high to ensure
master SPI operation.
 If an external device makes the SS pin low, the
SPI module stops working in master mode and
switches to slave mode by clearing the MSTR bit
 SPI Programming in AVR
in SPCR, and then sets the SPIF bit in SPSR.
 It is highly recommended to make the SS pin
output if you do not want to be interrupted when
you are working in master mode.
 When you are in slave mode, the SS pin is always
input and you cannot control it by software. You
should hold it externally low to activate the
SPI. When SS is driven high, SPI is disabled and
all pins of SPI are input. Also the SPI module
will immediately clear any partially received
data in the shift register. It can be used in
packet synchronizing by initiating and
terminating the data transfer.
 When you are working in slave mode and the SS
pin is driven high by an external device, the
SPI module is reset but not disabled and it is
not necessary to enable it again.
 SPI Programming in AVR using C
 Before you start data transmission, you should
set SPI Mode (Clock Polarity and Clock Phase)
by setting the values of the CPOL and CPHA bits
in SPCR.
 You can operate in either master or slave
modes.
Master operating mode
 If you want to work in master mode, you should
set the MSTR bit to one. Also you should set
SCK frequency by setting the values of SPI2X,
SPR1, and SPR2.
 Then you should enable SPI by setting the SPIE
bit to one before you start data transmission.
 Writing a byte to the SPI Data Register (SPDR)
starts data exchange by starting the SPI clock
generator.
 After shifting the last (8th) bit, the SPI
clock generator stops and the SPIF flag changes
to one.
 SPI Programming in AVR using C
 The byte in the master shift register and the
byte in the slave shift register are
exchanged after the last clock.
 Notice that you cannot write to the SPI Data
Register before transmission is completed,
otherwise the collision happens.
 To get the received data you should read it
from SPDR before the next byte arrives.
 We can use interrupts or poll the SPIF to
know when a byte is exchanged.
 As we mentioned before, in case of multibyte
burst write, the master continues to shift
the next byte by writing it into SPDR.
 If you want to signal the end of the packet,
you should pull high the SS pin.
SPI Programming in AVR

First Clock Edge LSB goes at end

Write an AVR program to initialize the SPI for master, mode 0, with CLCK
frequency = Fosc/16, and then transmit 0 to 255 via SPI repeatedly. The
received data should be displayed on Port A and send back the received no.
//////////////// SPI MASTER TRANSMITTER PROGRAM PAGE 1/2 ////////////////

# define F_CPU 1000000UL // define crystal frequency for delay.h

#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7

void SPI_MasterInit(void){
// Set MOSI, SCK and SS as Output Pins
DDRB |= (1<<MOSI) | (1<<SCK) | (1<<SS) ;
DDRB &= ~(1<<MISO); // Set MISO as an Input Pin
// Enable SPI, Master mode, Shift Clock = CLK /16
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
Write an AVR program to initialize the SPI for master, mode 0, with CLCK
frequency = Fosc/16, and then transmit 0 to 255 via SPI repeatedly. The
received data should be displayed on Port A and send back the received no.
///////////////// SPI MASTER TRANSMITTER PROGRAM PAGE 2/2 ////////////////

unsigned char SPI_MasterTransmit(unsigned char cData){

SPDR = cData; // Start transmission
while(!(SPSR & (1<<SPIF))); // Wait for transmission complete
return SPDR; // return the received data
}
int main()
{
unsigned char ch = 0; // data to send
DDRA = 0xFF; // PORTA is Output Port
SPI_MasterInit(); // Run as SPI Master
for(ch=0 ; ch<=255 ; ch++){ // infinite for loop for 0 to 255
_delay_ms(1000); // Call One Sec delay
// send and receive data and show received at PORTA
PORTA = SPI_MasterTransmit(ch);
}
return 0;
}
 SPI Programming in AVR
 When AVR is configured as a master, the SPI
will not control the SS pin. If you want to
make SS high or low, you have to do it by
writing 1 or 0, respectively, to the SS bit
of Port B. Slave operating mode
Slave Operating Mode
 When AVR is configured as a slave, the
function of the SPI interface depends on the
SS pin. If the SS is driven high, MISO is
tri-stated and the SPI interface sleeps. Only
the contents of SPDR may be updated in this
state.
 When SS is driven low, the data will be
shifted by incoming clock pulses on the SCK
pin.
 SPIF changes to one when the last bit of a
byte has been shifted completely. Notice that
the slave can place new data to be sent into
SPDR before reading the incoming data; this
is because in AVR there are two one-byte
buffers to store received data.
SPI Programming in AVR
Slave Operating Mode
 In slave mode there is no need to set SCK
frequency because the SCK is generated by the
master.
 But you must select the SPI mode (Clock Phase
and Clock Polarity) and Data Order to match
with SPI mode and Data Order of the other
side (master device).
 Finally you should enable the SPI by setting
the SPIE bit of SPCR to one. See Next Example
which is the slave version of Previous
Example.
Write an AVR program to initialize the SPI for slave, mode 0, and Show the
received data on Port A
////////////////////// SPI SLAVE PROGRAM PAGE 1/2 ///////////////////////

#define F_CPU 1000000UL // define crystal frequency for delay.h

#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7

void SPI_SlaveInit(void){
DDRB |= (1<<MISO); // Set MISO as an Output Pin
// Set MOSI, SCK and SS as Input Pins
DDRB &= ~(1<<MOSI) & ~(1<<SCK) & ~(1<<SS) ;
// Enable SPI as a Slave Device
SPCR = (1<<SPE);
}
Write an AVR program to initialize the SPI for slave, mode 0, and Show the
received data on Port A
////////////////////// SPI SLAVE PROGRAM PAGE 2/2 ///////////////////////
unsigned char SPI_SlaveReceive(unsigned char cData){
SPDR = cData; // send cData to master
// Wait for reception complete
while(!(SPSR & (1<<SPIF)));
// Return received data
return SPDR;
}

int main(){
DDRA = 0xFF; // PortA is Output
SPI_SlaveInit(); // configure as SPI Slave
while(1)
// send value of PORTA to Master and
// Show Received data at PORTA
PORTA = SPI_SlaveReceive(PORTA);
return 0;
}
MAX7221 Interfacing and Prog…
7-Segment Display:
 In many applications, when you want to
display numbers, 7-segments are the
best choice. These displays are made
of 7 LEDs to show different numbers
plus another LED to display the
decimal point.
 MAX7221 Interfacing and Prog…
 If you want to connect four 7-segment LEDs
directly to a microcontroller you need 4 x 8 =
32 pins. This is not feasible.
 The MAX7221 IC is supports up to eight 7-
segment LEDs. We can connect the MAX7221 to
the AVR chip using SPI protocol and control up
to eight 7-segment LEDs.
 The MAX7221 contains an internal decoder that
can be used to convert binary numbers to 7-
segment codes. That means we do not need to
refresh the 7-segment LEDs.
 All you need to do is to send a binary number
to the MAX7221, and the chip decodes the
binary data and displays the number.
 The device includes analog and digital
brightness control, an 8x8 static RAM that
stores each digit, and a test mode that forces
all LEDs on.
 MAX7221 Pins and Connections
 The MAX7221 is a 24-pin DIP
chip. It can be directly
connected to the AVR and con-
trol up to eight 7-segment
LEDs. A resistor or a
potentiometer is the only
external component that you
need. Next, we will discuss
the pins of the MAX7221.

GND: Pin 4 and pin 9 are the ground. These should

be connected to system ground
Vcc: Pin 19 is the VCC and should be connected to
the +5V.this pin is also the power to drive
the 7-segments and the connecting wire to this
pin should be able to handle 100-300 mA.
 MAX7221 Pins and Connections
ISET: Pin 18 is ISET and sets the
maximum segment current. This
pin should be connected to VCC
through a resistor. A 10KΩ
resistor can be connected to
this pin. If you want to
manually control the intensity
of the segments' light, you
can replace the resistor with
a 50KΩ potentiometer.
CS :Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR. Serial
data is loaded into the chip while CS is low,
and the last 16 bits of the serial data are
latched on CS's rising edge.
 MAX7221 Pins and Connections
DIN: Pin 1 is the serial data
input and should be connected
to the MOSI pin of the AVR. On
CLK's rising edge, data on
this pin is loaded into the
internal shift register.
Notice that the MAX7221 uses
the SPI Mode 0, that is, read
on rising edge and change on
falling edge..
CLK: Pin 13 is the serial clock input and should
be connected to the SCK pin of the AVR. On
MAX7221 the clock input is inactive when CS is
high.
DOUT: Pin 24 is the serial data output and is used
to connect more than one MAX7221 to a single
SPI bus.
 MAX7221 Pins and Connections
DIG0-DIG7:
The DIG pins are the 7-segment
selector pins and should be
connected to the 7-segments'
common cathode pin. The
MAX7221 chip can control up to
eight 7-segment LEDs. These
eight 7-segment dispalys are
designated as DIGO to DIG7.

SEGA…SEGG and DP: These pins select each segment

and should be connected to segments of each 7-
segment accordingly.
 MAX7221 data packet format
 In MAX7221, data packets are 16 bits long (two
bytes). You should first make CS low before
transmitting; then you transmit two bytes of
data and terminate the transmission by making
CS high.
 The first byte (MSBs) of each packet contains
the command control bits, and the second byte
is the data to be displayed.
 The upper four bits (D15-D12) of the command
byte are don't care and the lower four bits
(D11-D8) are used to identify the meaning of
the data byte to be followed.
 The second byte (D7-D0) of the two-byte packet
is called the data byte and is the actual data
to be displayed or control the 7-segment
driver.
 Table 17-3 shows the binary and hex values of
each command.
MAX7221 data packet format
MAX7221 data packet format
MAX7221 Interfacing and Prog…
#include <avr/io.h> //standard AVR header
#define SS 4
#define MOSI 5
#define SCK 7
void execute (unsigned char cmd, unsigned char
data){
// initializing the packet by pulling SS low
PORTB &= ~(1<<SS) ;
SPDR = cmd; // start CMD transmission
// wait cmd transfer to finish
while (!(SPSR & (1<<SPIF) ) );
// start DATA transmission
SPDR = data;
// wait data transfer to finish
while (!(SPSR & (1<<SPIF) ) ) ;
 MAX7221 Interfacing and Prog…
// terminate the packet by pulling SS high
PORTB |= 1<<SS;}
int main (void){
// MOSI, SCK and SS are output
DDRB = (1<<MOSI) | (1<<SCK) | (1<<SS) ;
// enable SPI as master, SCk = FOsc/16
SPCR = (1<<SPE) | (1<<MSTR)| (1<<SPR0);
execute(0x09,0x03); // decode only digit 0 and 1
execute(0x0B,0x02); // Set ScanLimit(upto digit 2)
execute(0x0A,0x0F); // max intensity
execute(0x0C,0x01); // Turn On Display
execute(0x01,0x07); // digit 0 is 7
execute(0x02,0x05); // digit 1 is 5
execute(0x03,0b00010111); // digit 2 is h
while(1); return 0;
}
MAX7221 Interfacing and Prog…

execute(0x09,0x03);