Conference Presentation SRAM Design
Conference Presentation SRAM Design
Conference Presentation SRAM Design
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie
Introduction
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie
SRAM Cell Design
Design equations for 6T SRAM:
1. Read Operation Stability
𝑊𝑎𝑐𝑐𝑒𝑠𝑠
𝐿𝑎𝑐𝑐𝑒𝑠𝑠
𝐶𝑒𝑙𝑙 𝑅𝑎𝑡𝑖𝑜= >1.28 ( 𝑅𝑒𝑎𝑑 𝑆𝑡𝑎𝑏𝑖𝑙𝑖𝑡𝑦 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛 ) ..(1)
𝑊𝑝𝑢𝑙𝑙𝑑𝑜𝑤𝑛
𝐿𝑝𝑢𝑙𝑙𝑑𝑜𝑤𝑛
2. Write Operation Stability
𝑊𝑝𝑢𝑙𝑙𝑢𝑝
𝐿𝑝𝑢𝑙𝑙𝑢𝑝
𝑃𝑢𝑙𝑙𝑢𝑝 𝑅𝑎𝑡𝑖𝑜= <1.6𝑉 ( 𝑊𝑟𝑖𝑡𝑒 𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛 𝑆𝑡𝑎𝑏𝑖𝑙𝑖𝑡𝑦 ) ..
Figure 1: 𝑊𝑎𝑐𝑐𝑒𝑠𝑠
M1, M3 are inverter pull down transistors. 𝐿𝑎𝑐𝑐𝑒𝑠𝑠
M2 and M4 are inverter pull up transistors. 3. Minimum Cell Area
M5 and M6 are NMOS access transistors.
BL is bit line and WL is word line.
Source: Wikipedia 4. Reverse Short Channel Effect
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie
SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE
• NMOS inverter = 110nM PMOS inverter = 220nM NMOS Access = 90nM
• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess=2.4
• Cbitline = 0.747fF for 512 cell array ( Interconnect Parasitics from ASU PTM Website )
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie
SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE
• NMOS inverter = 150nM PMOS inverter = 555nM NMOS Access = 180nM
• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess = 3 Cbitline = 0.747fF
• Curve shows SRAM cell is close to write failure.
• Bitline Precharge to less than 1.1V could be explored to increase SNM.
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie
Simulation Setup
V(ic) V(word)
V(write)
V(bit) V(bitbar)
V(qbar)
V(q)
• V(write) precharges Cbit to 0.8V via M7 V(write) – Applied to source of M7 (precharge switch)
V(bit)
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
PASS TRANSISTOR BASED TREE DESIGN
a2 a1
a2 a0
8 MSB BUFFERS
a2
a1
a2
a2 a1 in
a2 a0
a2 a1
a2
24 = 16 LSB Bits for Word Line Address from Column Buffers Directions of
Increasing bit number
From row buffer
To Word Line Buffer
From column buffer
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
PASS TRANSISTOR BASED TREE DESIGN
Delay
170 CK
W 880
160
158.9 L 50
150 IN OUT
140
CK
130
Delay (psec)
Identical Sizing for NMOS and PMOS to minimize charge injection effects
120 118.55
110
• Delay drops by ~40ps/2 for every
100 98.8 Doubling of transistor widths
90 89.3 • Delay drop saturates around
84.86
80 1000nM to 89ps
0 00 00 00 00 00 00 00 00 00 00 • Used W/L of 880/50 for final tree
2 4 6 8 10 12 14 16 18 20
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
TREE DECODER TIMING DIAGRAMS
The following waveforms were applied to the row and column selection inputs of the tree decoder
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
TREE DECODER TIMING DIAGRAMS
The top waveforms shows the matrix point output where the row and column select inputs are high
The output node discharges when the input goes low
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
SRAM TIMING CIRCUIT
Timing Sequence:
110 1. Disconnect Precharge
220
2. Enable Word Line
3. SAE / Write Enable
SAE/Write Enable 4. Wait for read/write
in
Precharge
Wordline Enable
5. Disble SAE/Write Enable
6. Disable Wordline
7. Reconnect Precharge
and discharge all word lines
Read/Write Input Pulse
Precharge Disable Pulse
Word Line Enable Pulse
Read/Write Output Pulse
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
READ WRITE CIRCUIT
( Design by Bong Jin )
Precharge Circuit
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
READ WRITE CIRCUIT TEST SETUP
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
READ / WRITE TIMING WAVEFORMS
Bitline
Bitline Bar
Data Output
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
SRAM Cell Layout
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
2X2 SRAM Array Layout
This unit can be replicated in all directions without any changes. LVS check remaining
Array Size = 3.7975umX2.4725um
B0 B0BAR B1 B1BAR
GND
WORD 1
VDD
WORD 0
GND
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
Final Waveforms and Decoder Layout
Left: Top waveform: Bitline and Bitline Bar waveforms for reading a 1 and Right: Layout of pass
Transistor based tree decoder
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
References
• Digital Integrated Circuits
Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic
( SRAM Cell Design, Decoders, Read Write Circuits )
• CMOS VLSI Design by Weste and Harris
( Butterfly Curves )
• CMOS Circuit Design, Layout and Simulation
Baker, Li, Boyce (Decoder Design)
• Course slides of Prof. Kia Bazargan
( Precharge Techniques, Decoders, SRAM Cell Design )
Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities
References (Contd.)
• Design of High Performance Microprocessor Circuits by Anantha Chandrakasan, William
Bowhill, Frank Fox
• A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage
and Virtual-Ground Replica Scheme
Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim, University of Minnesota
ISSCC 2007
• Digital Integrated Circuits by Jan Rabaey
• Large-Scale SRAM Variability Characterization in 45 nm CMOS
Zheng Guo, Student Member, IEEE, Andrew Carlson, Member, IEEE, Liang-Teck
Pang, Member, IEEE, Kenneth T. Duong, Tsu-Jae King Liu, Fellow, IEEE, Borivoje