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Introduction To Field Programmable Gate Arrays (Fpgas)

Field programmable gate arrays (FPGAs) are semiconductor chips that can be programmed to perform the function of nearly any digital circuit. FPGAs consist of an array of configurable logic blocks connected via a programmable interconnect. The configuration of the FPGA is defined by the user and can be modified by reprogramming, allowing the FPGA to take on different logic functions over its lifetime. More recent FPGAs have additional features like block RAM, digital signal processing blocks, and processor cores.

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46 views8 pages

Introduction To Field Programmable Gate Arrays (Fpgas)

Field programmable gate arrays (FPGAs) are semiconductor chips that can be programmed to perform the function of nearly any digital circuit. FPGAs consist of an array of configurable logic blocks connected via a programmable interconnect. The configuration of the FPGA is defined by the user and can be modified by reprogramming, allowing the FPGA to take on different logic functions over its lifetime. More recent FPGAs have additional features like block RAM, digital signal processing blocks, and processor cores.

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Senthil Kumar
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© © All Rights Reserved
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INTRODUCTION TO FIELD

PROGRAMMABLE GATE
ARRAYS (FPGAS)
FIELD PROGRAMMABLE ARRAYS
 The term FPGA stands for Field Programmable Gate Array and, it is a one type of  semiconductor logic
chip which can be programmed to become almost any kind of system or digital circuit, similar to PLDs. 
  The configuration of the FPGA architecture is generally specified using a language, i.e., HDL (Hardware
Description language) which is similar to the one used for an ASIC ( Application Specific Integrated
Circuit).
 Ability to re-configure FPGA to implement any digital logic function
 Partial re-configuration allows a portion of the FPGA to be continuously running while another
portion is being re-configured
 FPGAs also contain analog circuitry features including a programmable slew rate and drive strength,
differential comparators on I/O designed to be connected to differential signaling channels.
 Mixed-signal FPGAs contains ADCs and DACs with analog signal conditional blocks allowing them to
operate as a system-on-chip (SoC)
FPGA ARCHITECTURES
 Early FPGAs
N x N array of unit cells (CLB + routing)
 Special routing along center axis
 Next Generation FPGAs
M x N unit cells
 Small block RAMs around edges

 More recent FPGAs


 Added block RAM arrays
 Added multiplier cores
 Adders processor cores
FPGA ARCHITECTURE
 The general FPGA architecture consists of three types of modules. They are I/O blocks or Pads,
Switch Matrix/ Interconnection  Wires and Configurable logic blocks (CLB).

 he basic FPGA architecture has two dimensional arrays of logic blocks with a means for a user  to
arrange the interconnection between the logic blocks. The functions of an FPGA architecture
module are discussed below:

 CLB (Configurable Logic Block) includes digital logic, inputs, outputs. It implements the user
logic.
 Interconnects provide direction between the logic blocks to implement the user logic.
 Depending on the logic, switch matrix provides switching between interconnects.
 I/O Pads used for the outside world to communicate with different applications.
 Logic Block contains  MUX (Multiplexer), D flip flop and LUT. LUT implements the
combinational logical functions; the MUX is used for selection logic, and D flip flop stores the
output of the LUT
BASIC FPGA ARCHITECTURE

•More recent FPGA architectures have small block RAM arrays (usually placed in
center column), multipliers, processor cores, DSP cores w/ multipliers, and I/O cells
along columns for BGAs.
FPGA OPERATION
User writes configuration memory which
defines the function of the system. This
includes: the connectivity between the CLBs
and the I/O cells, the logic to be implemented
onto the CLBs, and the I/O blocks.

By changing the data in the configuration


memory, the function of the system changes as
well. This change in data can be implemented
at anytime during FPGA operation (run-time
configuration).
CONFIGURABLE LOGIC BLOCKS (CLBS)
ARCHITECTURE
 CLBs consist of:
 Look-up Tables (LUT) which implement the entries of a logic functions
truth table
 Some FPGAs can use LUTs to implement small Random Access Memory
(RAM)
 Carry and Control Logic
 Implements fast arithmetic operations (adders/ subtractors)
 Can be alsoconfigured for additional operations (Built-in-Self Test iterative-
OR chain)
 Memory Elements
 Configurable Flip Flops (FFs)/ Latches( Programmable clock edges, set/reset,
and clock enable)
 These memory elements usually can be configured as shift-registers
FPGA CONFIGURATION TECHNIQUES
 Full configuration and readback
 Simple configuration interface
 Automatic internal calculation of frame address
 Larger FPGAs have a longer download time
 Compressed configuration
 Requires multiple frame write capability
 Identical frames of configuration data are written to multiple frame addresses
 Extension of partial re-configuration interface capabilities
 Frame address is much smaller than frame of configuration data
 Reduces download time for initial configuration depending on
regularity of system function and the array percent that is utilized
 Partial re-configuration and readback
 Only change portions of configuration memory with respect to
reference design
 Reduces download time for re-configuration

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