Verilog Parameters and
Operators
Contents
Parameter in Verilog
Types of Parameters
Difference Between Specify and Module
Parameters
Localparam
Overriding module parameters
Verilog Operators
Operator Precedence
Interview Questions
Parameter in Verilog
Parameters are constants typically used to specify the
width of variables and time delays.
Syntax:
parameter identifier = constant_expression;
Example : Parameter lsb = 7 ;
parameter size = 8 ,
word = 32 ;
We cannot modify parameter values at runtime, but we
can modify a parameter value using
the defparam statement.
Types of Parameters
There are two types of parameters:
1. module parameters
2. specify parameters
Module Parameters
Module parameter can be used to override parameter
definitions within a module and makes the module have
a different set of parameters at compile time.
Example 1: module design_ip ( addr, wdata, write, sel, rdata);
parameter BUS_WIDTH = 32,
DATA_WIDTH = 64,
FIFO_DEPTH = 512;
input addr;
input wdata;
input write;
input sel;
output rdata;
wire [BUS_WIDTH-1:0] addr;
wire [DATA_WIDTH-1:0] wdata;
reg [DATA_WIDTH-1:0] rdata;
reg [7:0] fifo [FIFO_DEPTH];
endmodule
Example 2 :
module counter
# ( parameter N = 2, parameter DOWN = 0)
(input clk, input rstn, input en, output reg [N-1:0] out);
always @ (posedge clk) begin
if (!rstn) begin
out <= 0;
end else begin
if (en)
if (DOWN)
out <= out - 1;
else
out <= out + 1;
else
out <= out;
end
end
endmodule
Specify Parameters
These parameters are used to provide time and delay values
and declared using the 'specparam' keyword.
It is allowed to use both within the specified block and the
main module body.
Example :
// Use of specify block
Specify
specparam t_rise = 200, t_fall = 150;
specparam clk_to_q = 70, d_to_q = 100;
endspecify
// Within main module
module my_block ( );
specparam dhold = 2.0;
specparam ddly = 1.5;
parameter WIDTH = 32;
endmodule
Difference Between Specify and Module
Parameters
Specify parameter Module parameter
Specify the specparam keyword The module parameter is declared
declares parameter. by parameter.
It can be declared inside a specific It can only be declared within the
block or within the main module. main module.
This parameter may be assigned This may not be assigned
specparams and parameters. specparams.
SDF can be used to override Instance declaration parameter
values. values or defparam can be used to
override.
Localparam
A localparam is a constant that is similar to a parameter, but
which cannot be modified with a defparam, or by the ordered or
named parameter value assignment in a module instance
statement.
Local parameters can be assigned to a constant expression
containing a parameter that can be modified with the defparam,
or by the ordered or named parameter value assignment.
Syntax :
localparam name = value;
Example :
module adder(a,b,sum) ;
parameter height = 8;
parameter width = 10;
localparam length = 4;
input [width-1:0] a;
input [height-1:0] b;
input [length-1:0] c;
output [width-1:0] sum;
assign sum = a + b + c;
endmodule
module top;
reg [15:0] a;
reg [15:0] b;
wire [15:0] sum1;
adder #(.width(16), .height(4), .length(5) add_0 (a,b,sum2); //error as
length is not accessible outside the module adder
...
endmodule
Overriding module parameters
There are two methods to override a module parameter value during a module
instantiation.
1)By using the defparam keyword.
2)And module instance parameter value assignment.
By using the defparam keyword:
After the defparam keyword, the hierarchical path to the parameter is specified along with
the new value of the parameter.
Example : module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module inst_1(Clk, D, Q) ;
endmodule
module override ;
defparam top.inst_1.width = 7 ;
endmodule
By module instance parameter value
assignment:
The module instance parameter value
assignment method looks like an assignment of delay to
gate instance.
This method overrides parameters inside instantiated
modules, in the order, that they appear in the module.
Example : module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module #(7, 25) inst_1(Clk, D, Q) ;
endmodule
When one parameter depends on the other, remember
that if you change the first one, the second will
automatically be updated.
Example :
parameter width = 4 ;
parameter data = width / 10;
When 'width' changes, 'data' is automatically updated.
Verilog Operators
An operator, in many ways, is similar to a simple
mathematical operator. They receive one or two inputs and
generate a single output.
Operators enable synthesis tools to choose the desired
hardware elements.
Types of operators :
1. Arithmetic Operators
2. Logical Operators
3. Relational Operators
4. Bitwise Operators
5. Reduction Operators
6. Shift Operators
7. Conditional Operator
8. Concatenation Operator
9. Replication Operator
Arithmetic Operators
Logical Operators
Logical operators return either 0 or 1.
Relational Operators
Relational operators operate on numbers, and
return a Boolean value (true or false).
Bitwise Operators
Bitwise operators operate on bits, and return
a value that is also a bit.
Reduction Operators
Reduction operators accepts a single word
operand and produce a single bit as output.
Operates on all the bits within the word.
Shift Operators
Conditional Operator
Operator Precedence
precedence
increases
Interview Questions
How do I prevent selected parameters of a module from
being overridden during instantiation?
What is the difference between == and ===?
What is the difference between bit wise, unary and
logical operators?
