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Overview: Testability Evaluation: Outline

This document discusses testability evaluation and design for testability. It outlines quality policy considerations, testability measures like heuristic and probabilistic measures, and methods to calculate testability like Parker-McCluskey and cutting methods. Circuit types like sequential logic have lower testability than combinational logic. Solutions to improve testability include scan-path design strategies. Tradeoffs in design for testability include increased logic complexity and area versus lower defect levels. Testability criteria include testing costs and redesign costs.

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0% found this document useful (0 votes)
79 views46 pages

Overview: Testability Evaluation: Outline

This document discusses testability evaluation and design for testability. It outlines quality policy considerations, testability measures like heuristic and probabilistic measures, and methods to calculate testability like Parker-McCluskey and cutting methods. Circuit types like sequential logic have lower testability than combinational logic. Solutions to improve testability include scan-path design strategies. Tradeoffs in design for testability include increased logic complexity and area versus lower defect levels. Testability criteria include testing costs and redesign costs.

Uploaded by

jd47
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Overview: Testability Evaluation

Outline
• Quality Policy of Electronic Design
• Tradeoffs of Design for Testability
• Testability measures
• Heuristic measures
• Probabilistic measures
• Calculation of testability
• Parker - Mc Cluskey method
• Cutting method
• Conditional probabilities based method

Technical University Tallinn, ESTONIA


Design for Testability
The problem is - QUALITY:

Yield (Y) Defect level (DL)


Quality policy
P,n Pa

Design for testability P - probability of a defect


Testing n - number of defects
Pa - probability of accepting
a bad product

Y = (1 − P ) n
- probability of producing a good product

Technical University Tallinn, ESTONIA


Design for Testability
The problem is - QUALITY:

Yield (Y) Defect level (DL)


Quality policy
P,n Pa
n−m m
Pa n−m
(1− )
DL = = 1 − (1 − P ) = 1− Y n
= 1− Y n
= 1 − Y (1−T )
(1 − P ) + Pa
n

n - number of defects
m - number of faults tested
Pa = (1 − P ) − (1 − P )
m n

P - probability of a defect
Pa - probability of accepting a bad product
Y = (1 − P ) n
T - test coverage

Technical University Tallinn, ESTONIA


Introduction: The Problem is Money?
How to succeed?
Cost of quality
Cost
Try too hard!
How to fail?
Cost of Try too hard!
testing (From American Wisdom)

Test
Cost of coverage

Fault Coverage
the fault function
Time
Time

Conclusion:
Quality “The problem of testing
Optimum can only be contained
0% 100%
test / quality not solved”
T.Williams
Technical University Tallinn, ESTONIA
Design for Testability
The problem is - Money:
(1−T )
DL DL = 1 − Y
1 Y↓ Y(%)

90 8 5 1
T(%)
50 45 25 5
0 100
10 81 45 9
T(%)
Goal: DL ↓ ← T ↑ ← Testability ↑ 10 50 90
Paradox: Testability ↑ → DL ↑ (Y ↓)
Technical University Tallinn, ESTONIA
Design for Testability

Tradeoffs: DFT: Resynthesis or


Goal: DL ↓ ← T ↑ ← Testability ↑ adding extra hardware
Paradox: Testability ↑ → DL ↑ (Y ↓)

Performance ↓ Logic complexity ↑


Area ↑
Number of I/O ↑
Economic tradeoff:
C (Design + Test) < C (Design) + C (Test)
Power consumption ↑
Yield ↓

Technical University Tallinn, ESTONIA


Design for Testability
Economic tradeoff:

C (Design + Test) < C (Design) + C (Test)

C (DFT) + C (Test’) < C (Design) + C (Test)


C (Test) = CTGEN + (CAPLIC + (1 - Y) CTS ) Q
Test generation
Testing
Troubleshooting
Volume
Design
Product
C (DFT) = (CD + ΔCD) + Q(CP + ΔCP)
Technical University Tallinn, ESTONIA
Testability Criteria

Qualitative criteria for Design for testability:


Testing cost:
– Test generation time
– Test application time
– Fault coverage
– Test storage cost (test length)
– Availability of Automatic Test Equipment
Redesign for testability cost:
– Performance degradation
– Area overhead
– I/O pin demand

Technical University Tallinn, ESTONIA


Testability of Design Types
General important relationships:

• T (Sequential logic) < T (Combinational logic)


Solutions: Scan-Path design strategy
• T (Control logic) < T (Data path)
Solutions: Data-Flow design, Scan-Path design
strategies
• T (Random logic) < T (Structured logic)
Solutions: Bus-oriented design, Core-oriented design
• T (Asynchronous design) < T (Synchronous design)

Technical University Tallinn, ESTONIA


Testability of Design Types
T (Sequential logic) < T (Combinational logic)
Solutions: Scan-Path design strategy

IN OUT IN OUT
Combinationa Combination
l circuit al circuit

Scan-IN
q’ R q
q’ R q

Scan-OUT

Technical University Tallinn, ESTONIA


Testability of Design Types

T (Control logic) < T (Data path)


Control Part Solutions:
Scan-Path design strategie
Data-Flow design

y1 y2 y3 y4

a
R1 • c
M1 +
e
M3 R2 •
• b
• M2 • *
IN
d

Data Part

Technical University Tallinn, ESTONIA


Testability of Design Types
T (Random logic) < T (Structured logic)
Solutions: Bus-oriented design, Core-oriented design

Sea of gates

&
Sequence of
216 bits 16 bit 1
counter
System

Technical University Tallinn, ESTONIA


Testability Estimations for Circuit Types

Circuits less controllable Circuits less observable


• Decoders • Circuits with feedback
• Circuits with feedback • Embedded
• Counters – RAMs
• Clock generators – ROMs
• – PLAs
Oscillators
• Self-timing circuits • Error-checking circuits
• Self-resetting circuits • Circuits with redundant
nodes

Technical University Tallinn, ESTONIA


Bad Testability: Fault Redundancy
Redundant gates (bad design):
x1 Internal signal dependencies:
&
1
1 &
x2 & 1 y 1 1
&
1
x3 1
&
x4 & 1
&

y = x1 ∨ ( x1 ∨ x2 ) x4 ∨ x3 x4 Impossible pattern,
OR → XOR is not testable
∂y Faults at x2 is not testable
≡0
∂x2 Optimized function: y = x1 ∨ x4 ∨ x3
Technical University Tallinn, ESTONIA
Bad Testability: Fault Redundancy

Hazard control circuitry: Error control circuitry:


1
0→1
0→1 & Decoder

1→0 1
1 & 1
≡ 1
& ⊕
1 E
≡ 0
Redundant AND-gate
Fault ≡ 0 is not testable E ≡ 1 if decoder is fault-free
Fault ≡ 0 is not testable

Technical University Tallinn, ESTONIA


Testability Measures

Evaluation of testability:
Controllability for 1 needed
• Controllability
• C0 (i)
1 i 1
• C1 (j) 2 & 2 Y
20 &
• Observability k 20
1 j &
• OY (k) 2 1 1
• OZ (k) 20 2 Z
x 20 1
• Testability
Defect
Probability of detecting 1/260

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Controllability calculation:
Value: minimum number of nodes that must be set in order to produce 0 (or 1)
For inputs: C0(x) = C1(x) = 1
For other signals: recursive calculation starting from inputs

C0(x1) = 1 C0(x31 ) = 23
C0(x33 ) = min [C0(x31 ), C0(x32 ) ] + 1 =
&
C0(x2) = 1 = min (23,11) + 1 = 12

C0(x32 ) = 11

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Controllability calculation:
Value: minimum number of nodes that must be set in order to produce 0 (or 1)
For inputs: C0(x) = C1(x) = 1
For other signals: recursive calculation starting from inputs

C0(x1) = 1 C0(x31 ) = 23

1 C0(x33 ) = C0(x31 ) + C0(x32 ) + 1 = =


C0(x2) = 1 23 + 11 + 1 = 35
C0(x32 ) = 11

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Controllability calculation:
Value: minimum number of nodes that must be set in order to produce 0 (or 1)
For inputs: C0(x) = C1(x) = 1
For other signals: recursive calculation starting from inputs

C0(x31 ) = 23
C0(x1) = 1 C1(x31 ) = 18
C0(x33 ) = min { [ C0(x31 ) + C0(x32 ) ],
⊕ [C1(x31 ) + C1(x32 ) ] } + 1 = min{
C0(x2) = 1
(23 +12), (18 + 20) } + 1 = min
C0(x32 ) = 12 (35,38) + 1 = 36
C1(x32 ) = 20

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Controllability calculation:
Value: minimum number of nodes that must be set in order to produce 0 or 1
For inputs: C0(x) = C1(x) = 1
For other signals: recursive calculation rules:
x1 C0(y) = min{C0(x1), C0(x2)} + 1
x & y x2 & y
C1(y) = C1(x1) + C1(x2) + 1

C0(y) = C1(x) + 1 x1 C1(y) = min{C1(x1), C1(x2)} + 1


C1(y) = C0(x) + 1 1 y
x2 C0(y) = C0(x1) + C0(x2) + 1

x1 C0(y) = min{(C0(x1) + C0(x2)), (C1(x1) + C1(x2))} + 1


x2 ⊕ y
C1(y) = min{(C0(x1) + C1(x2)), (C1(x1) + C0(x2))} + 1

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Observability calculation:
Value: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
For other signals: recursive calculation starting from inputs

O(x31 ) = O(x33 ) + C1(x32 ) = =


23 + 11 + 1 = 35
O(x33 ) = 23
&
O(y) = 1
C1(x32 ) = 11

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Observability calculation:
Value: minimum number of nodes which must be set for fault propagating
For outputs: O(y) = 1
For other signals: recursive calculation rules:
x1
x2 & y O(x1) = O(y) + C1(x2) + 1
x & y
x1
O(x) = O(y) + 1 1 y O(x1) = O(y) + C0(x2) + 1
x2

x1
x2 ⊕ y O(x1) = O(y) + 1

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
T(x ≡ 0) = C1(x) +
Testability calculation:
O(x)
Value: sum of controllability and observability
T(x ≡ 1) = C0(x) +
O(x)
T(x31 = 0) = O(x31 ) + C1(x31 ) = 35 + 16 = 51

O(x31 ) = 35

C1(x31 ) = 16 O(x33 ) = 23
&
O(y) = 1
C1(x32 ) = 11

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Controllabilies Obs.
Controllability and observability: x C0(x) C1(x) O(x)
1 1 1 10
Macro 2 1 1 12
1
&
3 1 1 11
2 & d 4 1 1 11
71
a 5 1 1 10
&
3 7 72 e 6 1 1 10
& b
4 & 7 3 2 9
& y 71 3 2 11
5
73 72 3 2 9
&
c 73 3 2 9
6 a 4 2 9
b 4 2 7
c 4 2 7
d 4 2 7
e 5 5 4
y 8 5 1

Technical University Tallinn, ESTONIA


Heuristic Testability Measures
Testability calculation: Controllabilies Obs. Testab.
T(x ≡ 0) = C1(x) + x C0(x) C1(x) O(x) T(x≡0)
O(x) 1 1 1 10 11
2 1 1 12 13
T(x ≡ 1) = C0(x) + 3 1 1 11 12
4 1 1 11 12
O(x) 5 1 1 10 11
1 Macro 6 1 1 10 11
2 & d 7 3 2 9 11
&
71 71 3 2 11 13
a
&
72 3 2 9 11
3 7 72 e 73 3 2 9 11
& b
4 & a 4 2 9 11
& y b 4 2 7 9
5
73 c 4 2 7 9
&
c d 4 2 7 9
6 e 5 5 4 9
y 8 5 1 6

Technical University Tallinn, ESTONIA


Probabilistic Testability Measures
Controllability calculation:
Value: minimum number of nodes that must be set in order to produce 0 or 1
For inputs: C0(i) = p(xi=0) C1(i) = p(xi=1) = 1 - p(xi=0)
For other signals: recursive calculation rules:
x1
x2 & y py= px1 px2
x & y
py = 1 - px
x1
1 y py= 1 - (1 - px1 )(1 - px2 )
x2

n n
x1 x1
& y p y = Π p xi 1 y p y = 1 − Π (1 − p xi )
..

..

xn xn
.

i =1 i =1

Technical University Tallinn, ESTONIA


Probabilistic Testability Measures
Probabilities of reconverging fanouts:
x1
⊕ y py = (1 – px1 ) px2 + (1 – px2 ) px1
x2
= 0,25 + 0,25 = 0,5
x1 a
x2 & py = 1 - (1 - pa ) (1 - pb)
1 y
= 1 - 0,75*0,75 = 0,44
&
b

Signal correlations:

x & py= px px = px2 ?


y

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
py = 1 - (1 - pa ) (1 - pb) =
Parker - McCluskey
= 1 - (1 - px1 (1 - px2 ))(1 - px2 (1 - px1 )) =
algorithm:
= 1 - (1 - px1 + px1 px2 ) (1 - px2+ px1 px2 ) =
= 1 – (1 - px2+ px1 px2 - px1 + px1 px2 - p2x1 px2 +

x1 a + px1 px2 - px1 p2x2 + p2x1 p2x2 ) =


x2 &
= 1 – (1 - px2+ px1 px2 - px1 + px1 px2 - px1 px2 +
1 y
& + px1 px2 - px1 px2 + px1 px2 ) =
b
= px2- px1 px2 + px1 - px1 px2 + px1 px2 -
- px1 px2 + px1 px2 - px1 px2 ) =
= px1 + px2 - 2px1 px2 = 0,5
Technical University Tallinn, ESTONIA
Calculation of Signal Probabilities
Straightforward methods:
1 Calculation gate by gate:
21 & a
2 pa = 1 – p1p2 = 0,75,
& c pb = 0,75, pc = 0,4375, py = 0,22
22
&
b Parker - McCluskey algorithm:
3 y
&
py = pcp2 = (1- papb) p2 =
23
= (1 – (1- p1p2) (1- p2p3)) p2 =

For all inputs: pk = 1/2 = p1p2 2 + p22p3 - p1p23p3 =


= p1p2 + p2 p3 - p1p2p3 = 0,38

Technical University Tallinn, ESTONIA


Probabilistic Testability Measures
Parker-McCluskey: Observability:
p(∂ y/∂ a = 1) = pb p2 =
1
21 & a
2 = (1 - p2p3) p2 = p2 - p22p3
x
& c = p2 - p2p3 = 0,25
22
& Testability:
3
b y
&
p(a ≡ 1) = p(∂ y/∂ a = 1) (1 - pa) =
23
= (p2 - p2p3)(p1p2) =

For all inputs: pk = 1/2 = p1p22 - p1p22p3 =


= p1p2 - p1p2p3 = 0,125

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
Cutting method
1
2 & d
&
Idea: 71
a
• Complexity of exact 3
& e
7 72
calculation is reduced by 4
&
& b
using lower and higher & y
5
bounds of probabilities 73
c
Technique: &
6
• Reconvergent fan-outs are
cut except of one
• Probability range of [0,1] is
assigned to all the cut lines Lower and higher bounds for the
• The bounds are propagated probabilities of the cut lines:
by straightforward p71 := (0,1), p72 := (0,1)
calculation

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
1
1/2 1/2 &
• For all inputs: pk = 0,5 2
[0,1] 71 & d
[1/2,3/4]
Cutting method
• Reconvergent fan-outs are a
cut except of one – 71 and [1/2,1] &
72 3 7 72 e
Probability range of [0,1] is
& b [1/4,3/4]
• 4 &
assigned to all the cut 3/4
[1/2,1] y [34/64,54/64]
lines - 71 and 72 5 &
• The bounds are 73
propagated by 3/4 & c Exact value:
straightforward calculation
6 5/8 41/64
1/2

Calculation steps:
pk [pLB , pHB) Exact pk pk [pLB , pHB) Exact pk
p7 3/4 3/4 pb [1/2, 1] 5/8
p71 [0, 1] 3/4 pc 5/8 5/8
p72 [0, 1] 3/4 pd [1/2, 3/4] 11/16
p73 3/4 3/4 pe [1/4, 3/4] 19/32
pa [1/2, 1] 5/8 py [34/64, 54/64 ] 41/64

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
Method of conditional
probabilities Probabilitiy for – y
Conditions – x ∈ set of conditions

x y
p( y ) = ∑ p( y /( x = i) p( x = i)
i∈( 0 ,1)

P(y) = p(y/x=0) p(x=0) + p(y/x=1) p(x=1)


Conditional probabilitiy
Idea of the method:
Two conditional probabilities are calculated along the paths (NB! not bounds as in
the case of the cutting method)
Since no reconvergent fanouts are on the paths, no danger for signal correlations

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
1
Method of conditional 2 &
& d
71 [1/2,3/4]
a
probabilities [1,1/2] &
3 7 72 e
p( y ) = ∑ p( y /( x = i) p( x = i)
i∈( 0 ,1)
4
&
3/4 & b
[1,1/2]
[1/2,5/8]

& y
5
73
&
c
[1/2,11/16]
6 [1,1/2]
x y
* ** * **
Pk [P k , P k ] Pk [P k , P k ]
P7 Pb [1, 1/2]
NB! Probabilities P71 Pc [1, 1/2]
Pk = [Pk* = p(xk/x7=0), Pk ** = p(xk/x7=1)] P72 Pd [1/2, 3/4]
P73 Pe [1/2, 5/8]
are propagated, not bounds
Pa [1, 1/2] Py [1/2, 11/16 ]
as in the cutting method.
For all inputs: pk = 1/2
py = p(y/x7=0)(1 - p7) + p(y/x7=1)p7 = (1/2 x 1/4) + (11/16 x 3/4) = 41/64

Technical University Tallinn, ESTONIA


Calculation of Signal Probabilities
Using BDDs: 1
21 & a
2 For all inputs: pk = 1/2
py = p(L1) + p(L2) =
& c
= p1 p21 p23 + (1 - p1) p22 p3 p23 = 22
&
b y
= p1 p2 + p2 p3 - p1p2 p3 = 0,38 3 &

23
p1 p21 p23
y L1
1 21 23 y p2 p1
L2 2 1

22 3
3
(1-p1)p22p3p23 p2(1-p1)p3

Technical University Tallinn, ESTONIA


Calculating Probabilities on BDDs

1
21 & a
py = Σ Π px 2

22 & c
Lk∈L(1) x∈Xk &
3 b y
&
23

Example: L1
y
1 21 23
L1 = (1,21,23) L2
L2 = (1,22,3,23) 22 3

py = p1p2 + p1p2p3 = 0,375


Technical University Tallinn, ESTONIA
Heuristic and Probabilistic Measures

Heuristic controllability measure:

CC1[y] = min { Σ CC1 (x(m) } + const.


k: lk∈L(1) m∈Mk

Probabilistic measure: y
L1
1 21 23
py = Σ Π px L2
22 3
k: Lk∈L(1) x∈Xk

Technical University Tallinn, ESTONIA


Heuristic Controllabilities
Using BDDs for controllability 1
21 & a
calculation: 2
Gate level calculation
BDD-based algorithm x C0(x) C1(x) & c
for the heuristic a 3 2 22
measure is the same &
b 3 2 b y
as for the probabilistic 3 &
c 5 4
measure
y 2 6 23

C1(y) = min [(C1(L1), C1(L2)] + 1 =


y L1
3 3 1
= min [C1(x1) + C1(x2), 1 21 23

C0(x1) + C1(x2) + C1(x3)] + 1 = L2


22 3
= min [2, 3] + 1 = 3 3 3

Technical University Tallinn, ESTONIA


Probabilistic Testability Measures
1
Using BDDs: 21 & a
2
x
Observability:
& c
p(∂ y/∂ x21 = 1) = p(L1) p(L2) p(L3) = 22
&
b y
= p1 p23 (1 - p3) = 0,125 3 &

23
Testability:
L1 L2
p(x21 ≡ 0) = p21 p(∂ y/∂ x21 = 1) = y
1 21 23
= p21 p(L1) p(L2) p(L3) =
= p2p1 (1 - p3) = 0,125 22 3
Why: p(∂ y/∂ x21 = 1) = p21 p(∂ y/∂ x21 =
L3
1)?
Technical University Tallinn, ESTONIA
Calculating Observabilities on BDDs

1 Macro
y
2 & d 6 73
71 & a
3 7 72
& e
4
& b 1 5
&
y
5 &
73
c
& 2 71 72
6

∂y/∂x(m) = L(m0,m) ∧L(m1, mT,1 ) ∧L(m0, mT,0 )

p(∂y/∂x(m)=1)=p(m0,m) ∧p(m1,mT,1 ) ∧p(m0,mT,0 )

Technical University Tallinn, ESTONIA


Calculating Observabilities on BDDs

1 Macro
2 & d Calculation procedure:
71 & a
3 & e 6 73 5 2
7 72 1/64
4
& b
& 5 2
y 1/64
5 &
73 6
c 2
& 1/64
6 2
1/64
5 2
y 4/64
6 73 5 2 7
1
1/64
72 2
5 1/64
1
2
1/64
2 71 72
p(∂ y/∂ x1= 1) = 11/64
Technical University Tallinn, ESTONIA
Calculation of Signal Probabilities
Combining BDDs and conditional probabilities

w
x
y

Using BDDs gives correct results only inside the blocks,


not for the whole system
New method:
• Block level: use BDDs and straightforward calculation
• System level: use conditional probabilities

Technical University Tallinn, ESTONIA


Register Transfer Level and DDs

Superposition of word-level DDs:


R2 0
y4 #0
y1 y2 y3 y4
1 R2
a 2 0 0
R1 • c y3 y1 R1 + R 2
M1 + 1
e IN + R 2
M3 R2 • 1
b IN

M2 * 2
IN • • R1
d
3 0
y2 R1 * R 2
1
IN* R2

Technical University Tallinn, ESTONIA


Calculating RT-level Probabilities

Gate-level calculation: Terminal nodes


data-path):
py = Σ Π px R2 0
y4 #0
1
Lk∈L(1) x∈Xk R2
2 0 0
RT-level calculation: y3 y1 R1 + R 2
1
P(R=IN) = Σ Π P(x=e) 1
IN + R 2
IN
2
R1
Li∈L(IN,R) x∈Xi 3 0
y2 R1 * R 2
Example:
1
IN* R2
P(R2=IN) = P(y4=2) P(y3=1)

Technical University Tallinn, ESTONIA


Calculating RT-Level Observabilities

Gate-level calculation: Terminal nodes


data-path):
py = Σ Π px R2
y4 0 #0
1
Lk∈L(1) x∈Xk R2
2 0 0
RT-level calculation: y3 y1 R1 + R2
1
P(y=z(m )) = Σ
T
Π P(x=e) 1
IN + R2
IN
2
R1
Li∈L(m0,m ) x∈Xi
T
3 0
y2
Example: R1 * R2
1
IN* R2
P(R2= R1∗ R2) = P(y4=2) P(y3=3) P(y2=0)

Technical University Tallinn, ESTONIA


Calculating RT-level Probabilities

Gate-level calculation: Nonterminal nodes


py = p(y=1) = Σ Π px (control-path):

0
Lk∈L(1) x∈Xk q q′ #1
0
RT-level calculation: 1
xA #4

1
#2
P(y=k) = Σ Π P(x=e) 2 0
xB #5

1
Li∈L(k) x∈Xi 3,4 #3
Example:
P(q=5) = P(q=2)P(xB=0) + P(q=3) + P(q=4)

Technical University Tallinn, ESTONIA

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