Fall 2020 ECE 445 - Computer Organization 1

THE MIPS ONE-BUS

IMPLEMENTATION
ECE 445 – Computer Organization
Dr. Craig Lorie
Electrical and Computer Engineering
Lecture #7
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Topics Covered
• Datapath for the MIPS One-bus implementation
• Internal CPU bus
• Datapath components
• Control unit for the MIPS One-bus implementation
• Tri-state buffers
• Control signals
• Instruction Cycle
• Fetch, decode, execute
• Instruction processing on the MIPS One-bus implementation
• Instruction Fetch
• Execute: ADD instruction
• Execute: LOAD WORD instruction
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Reading Assignment
• Hennessey/Patterson: 4.1 – 4.4
• Hennessey/Patterson: 3rd Edition, 5.5 (on Blackboard)
• Additional reading posted on Blackboard.
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PROCESSOR DESIGN
Datapath and Control Unit
Internal busses.
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Computer Organization
• The processor can be partitioned into the:

1. Datapath
• Composed of functional blocks.
• Implements the actions necessary to fetch and execute all of the
instructions specified in the instruction set of the processor.

2. Control Unit
• Generates the control signals.
• Controls the components in the datapath.
• Value of each control signal determined during instruction decoding.
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Processor Design
• Design both the datapath and the control unit.
• Consider all instructions that are executed by the processor.
• Determines the components required in the datapath.
• Determines the required control signals.
• Consider cost, performance, and power consumption.
• Determines technology choice.
• Determines component selection.
• Design a family of processors.
• All processors adhere to the specified instruction set architecture (ISA).
• Each is designed to meet a different cost/performance/power
consumption specification.
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Internal CPU Bus

• In principle we must make connections between datapath
components for every instruction.
• This, potentially, leads to all datapath components being connected to all
other datapath components.
• Numerous connections are expensive and take up valuable
space on the chip.
• Instead, use a set of wires that all components can connect to
and share in order to transfer information.
• Rather than using a dedicated set of wires between every pair of
datapath components.
• Results in a bus-based design for the datapath of the processor.
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DATAPATH
MIPS One-bus implementation.
Using one internal bus.
Datapath components: ALU, Register File, etc.
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MIPS: One-bus Organization

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Internal Bus

• The One-bus organization of the MIPS architecture uses a single 32-bit bus
to interconnect all of the datapath components.
• Data is transferred between datapath components in 32-bit words.
• Registers are 32-bits wide.
• ALU operands are 32-bits wide.
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Register File

• Realizes the register set specified in Write Register # Read Register #

the MIPS architecture. 5-bit field 5-bit field

• Thirty-two 32-bit registers. Specifies the Specifies a source
• Two ports (read, write). destination register. register.
Either Rt or Rd field Either Rs or Rt field
of instruction. of instruction
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Write Register Multiplexer

• Destination register specified in Rd or Rt. Field Name Instruction Register

• Write register multiplexer selects the Rt(4..0) IR(20..16)
appropriate register field to specify the
Rd(4..0) IR(15..11)
destination register.
• 2-to-1 Multiplexer
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Read Register Multiplexer

• Source register specified in Rs or Rt. Field Name Instruction Register

• Read register multiplexer selects the Rs(4..0) IR(25..21)
appropriate register field to specify a
Rt(4..0) IR(20..16)
source register.
• 2-to-1 Multiplexer
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Arithmetic and Logic Unit (ALU)

• Implements arithmetic and logic operations.

• Takes two 32-bit operands and produces a 32-bit result (and overflow).
• The ALU is combinational logic.
• Does not require a clock.
• Does not store information.
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Temporary Registers

• 32-bit registers.
• Register A stores one ALU operand (input).
• Register B stores the other ALU operand (input).
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Program Counter (PC)

• 32-bit register.
• Stores the address of the instruction to be fetched from (program) memory.
• Realizes the program counter (PC) specified in the MIPS architecture.
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Instruction Register (IR)

Instruction Register Field Name

• 32-bit register.
IR(31 – 26) opcode(5 – 0)
• Stores the instruction being executed by
IR(25 – 21) Rs(4 – 0)
the processor.
IR(20 – 16) Rt(4 – 0)
• Previously fetched from memory.
• Realizes the IR specified in the MIPS arch. IR(15 – 11) Rd(4 – 0)
IR(15 – 0) Imm(15 – 0)
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Memory Address Register (MAR)

• 32-bit register.
• Stores the address of the data to be read from or written to (data) memory.
• Part of the bus interface logic.
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Memory Data Register (MDR)

• 32-bit register.
• Stores the data read from or written to (data) memory.
• Part of the bus interface logic.
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Sign Extension Unit (SEU)

• Sign-extends the 16-bit immediate value to 32 bits.

• Extends the sign bit from bit 15 to bit 31.
• Maintains the sign of the immediate operand (in the MIPS I-type instruction).
• The ALU is combinational logic.
• Does not require a clock.
• Does not store information.
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Control Unit

• Decodes the instruction that is in the Instruction Register (IR).

• Opcode field (for all instructions).
• Funct field (for R-type instructions only).
• Generates the control signals (for the datapath).
• Asserts the appropriate control signals for the instruction being executed.
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One-bus Organization (Limitations)

• Consider the following MIPS • Which of these instructions can be

instructions: executed on this implementation
• R-type instructions of the MIPS processor?
• Add Immediate • Which cannot?
• Load Word, Store Word • What modifications should be
• Branch and Jump instructions made to the processor?
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CONTROL UNIT
Decodes instruction. Generates control signals.
Enable (EN) and Output Enable (OE) control signals.
Control signals required for the MIPS one-bus implementation.
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MIPS (One-bus): Control Unit

• Decodes the instruction that is in the Instruction Register (IR).

• Opcode field (for all instructions).
• Funct field (for R-type instructions only). Control signals can be
• Generates the control signals (for the datapath). active-high or active-low.
• Asserts the appropriate control signals for the instruction being executed .
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EN and OE Control Signals

To internal bus

Register (flip-flop) with Enable Tri-state buffer

To internal bus
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Register File

Datapath
Component Signal Description
Register File RFEN When asserted, RF inputs data from CPU bus.
RFOE When asserted, RF tri-state buffer is enabled and
RF outputs data to CPU bus.
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Write Register Multiplexer

Datapath
Component Signal Description
Write register Mux RDorRT RDorRT = 0: Use Rd field to specify destination reg.
RDorRT = 1: Use Rt field to specify destination reg.
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Read Register Multiplexer

Datapath
Component Signal Description
Read register Mux RSorRT RSorRT = 0: Use Rs field to specify source register.
RSorRT = 1: Use Rt field to specify source register.
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Arithmetic and Logic Unit (ALU)

Datapath
Component Signal Description
ALU ALUOE When asserted, ALU tri-state buffer is enabled and
ALU outputs data to CPU bus.
ALUCNTL Controls the operation performed by the ALU.
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Temporary Registers

Datapath
Component Signal Description
Register A AEN When asserted, Reg A inputs data from CPU bus.
Register B BEN When asserted, Reg B inputs data from CPU bus.
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Sign-Extension Unit (SEU)

Datapath
Component Signal Description
Sign-extension Unit SEUOE When asserted, SEU tri-state buffer is enabled and
SEU outputs data to CPU bus.
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Program Counter

Datapath
Component Signal Description
Program Counter PCEN When asserted, PC inputs data from CPU bus.
PCOE When asserted, PC tri-state buffer is enabled and PC
outputs data to CPU bus.
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Instruction Register

Datapath
Component Signal Description
Instruction Register IREN When asserted, IR inputs data from CPU bus.
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Memory Address Register (MAR)

Datapath
Component Signal Description
Memory Address Reg MAREN When asserted, MAR inputs data from CPU bus.
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Memory Data Register (MDR)

Datapath
Component Signal Description
Memory Data Reg MDREN When asserted, MDR inputs data from CPU bus.
MDROE When asserted, MDR tri-state buffer is enabled and
MDR outputs data to CPU bus.
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MIPS (One-bus): Control Signals

Datapath
Component Signal Description
Program Counter PCEN When asserted, PC inputs data from CPU bus.
PCOE When asserted, PC tri-state buffer is enabled and PC
outputs data to CPU bus.
Instruction Register IREN When asserted, IR inputs data from CPU bus.
Register A AEN When asserted, Reg A inputs data from CPU bus.
Register B BEN When asserted, Reg B inputs data from CPU bus.
Memory Address Reg MAREN When asserted, MAR inputs data from CPU bus.
Memory Data Reg MDREN When asserted, MDR inputs data from CPU bus.
MDROE When asserted, MDR tri-state buffer is enabled and
MDR outputs data to CPU bus.

• PC and MDR require bi-directional data transfer via the internal CPU bus.
• All other registers only need to read (input) from the internal CPU bus.
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MIPS (One-bus): Control Signals

Datapath
Component Signal Description
Register File RFEN When asserted, RF inputs data from CPU bus.
RFOE When asserted, RF tri-state buffer is enabled and
RF outputs data to CPU bus.
Read register Mux RSorRT RSorRT = 0: Use Rs field to specify source register.
RSorRT = 1: Use Rt field to specify source register.
Write register Mux RDorRT RDorRT = 0: Use Rd field to specify destination reg.
RDorRT = 1: Use Rt field to specify destination reg.
Sign-extension Unit SEUOE When asserted, SEU tri-state buffer is enabled and
SEU outputs data to CPU bus.
ALU ALUOE When asserted, ALU tri-state buffer is enabled and
ALU outputs data to CPU bus.
ALUCNTL Controls the operation performed by the ALU.
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MIPS (One-bus): ALU and Memory

ALU Control signals Memory Control signals
ALUCNTL Operation Signal Operation
0000 AND Read When asserted, data is
transferred from memory.
0001 OR
Write When asserted, data is
0010 Add transferred to memory.
0110 Subtract
Both cannot be asserted at the same time.
0111 Set on Less Than
0011 Increment by 4
Signal Operation
A maximum of 16 operations can R/W’ When low (0), data is transferred
be defined for the ALU. to memory. (write)
(using a 4-bit control signal) When high (1), data is
transferred from memory. (read)
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INSTRUCTION CYCLE
Fetch, decode, and execute.
Processor clocking.
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Instruction Cycle
• Each machine language instruction is processed according to
the steps in the instruction cycle.
• Aka. the fetch-execute cycle and the CPU cycle.

Instruction
Fetch

Instruction
Decode

Execute

Instruction Cycle
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Instruction Cycle: Fetch

• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Instruction Fetch
• PC contains address of ML instruction.
• Read (fetch) instruction from program
memory at address pointed to by PC.
ID
• Adjust PC to point to next instruction.
• Increment PC (by 4 for MIPS)
• Use Branch target address

EX • Use Jump target address

Instruction Cycle
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Instruction Cycle: Decode

• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Instruction Decode
• Instruction is identified by the opcode
(and the funct bits for MIPS R-type
instructions).
ID • Control unit decodes instruction.
• Appropriate control signals are generated.
• Control the functional units in the datapath

EX needed to execute the instruction.

• Control unit generates a different set of control
Instruction Cycle signals for different instructions.
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Instruction Cycle: Execute

• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Execute
• Functional units in the datapath
implement the required actions for the
executed instruction.
ID • Functional units controlled by the control
signals.
• Different instructions require a different set
of actions and, thus, a different set of
EX functional units.

Instruction Cycle
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Processor Clock Cycles

• Processor operation is governed by a constant-rate clock.
• Instruction cycle is, thus, controlled by the clock as well.
• Each step in the instruction cycle requires one clock cycle.
• Instruction processing described using register transfer language (RTL).

Clock period

Clock (cycles)

Data transfer
and computation

Update state

TCLK = clock period (clock cycle time)

FCLK = clock frequency (clock rate)
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Processor Clocking
• Operation of the CPU is governed by a constant-rate clock.

Clock period

Clock (cycles)

Data transfer
and computation

Update state

• Data is transferred from one register to

another on the internal bus. Registers are updated on the
• Calculations are carried out by the ALU. rising-edge of the clock.
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INSTRUCTION PROCESSING
Instruction Fetch
Execute: Add instruction
Execute: Load Word instruction
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MIPS: One-bus Organization

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MIPS (One-bus): Instruction Fetch

• Using RTL, specify the micro-operations needed to implement the
instruction fetch on the MIPS One-bus organization.
• Identify the control signals that must be asserted for each micro-operation.
• Specify the value where necessary.

Clock
Cycle RTL Description Control Signals
1 MAR <- PC Copy contents of PC to MAR. MAREN, PCOE
2 MDR <- M[MAR] Read contents of memory into Read
MDR (using System Bus).
3 IR <- MDR Transfer contents of MDR to IR. IREN, MDROE
4 A <- PC Copy contents of PC to Reg A. AEN, PCOE
5 PC <- A + 4 Increment A by 4 and store in PC. PCEN, ALUCNTL = 0011
• Can the instruction fetch be implemented in fewer clock cycles?
• Which micro-operations can be completed in the same clock cycle?
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MIPS (One-bus): Add

• Using RTL, specify the micro-operations needed to execute the add
instruction on the MIPS One-bus organization.
• Assume that the instruction has been fetched and is in the IR.
• Identify the control signals that must be asserted for each micro-operation.
• Specify the value where necessary.

Clock
Cycle RTL Description Control Signals
1 A <- RF[Rs] Transfer contents of Rs register AEN, RFOE, RSorRT = 0
in RF to Reg A.
2 B <- RF[Rt] Transfer contents of Rt register BEN, RFOE, RSorRT = 1
in RF to Reg B.
3 RF[Rd] <- A + B Add A and B and store result in RFEN, RDorRT = 0, ALUOE,
Rd register in RF. ALUCNTL = 0010
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MIPS (One-bus): Load Word

• Using RTL, specify the micro-operations needed to execute the load word
instruction on the MIPS One-bus organization.
• Assume that the instruction has been fetched and is in the IR.
• Identify the control signals that must be asserted for each micro-operation.
• Specify the value where necessary.

Clock
Cycle RTL Description Control Signals
1 A <- RF[Rs] Transfer contents of Rs register AEN, RFOE, RSorRT = 0
in RF to Reg A.
2 B <- SignExt[Imm] Sign-extend immediate value BEN, SEUOE
and store in Reg B.
3 MAR <- A + B Add A and B and store in MAR. MAREN, ALUOE, ALUCNTL = 0010
4 MDR <- M[MAR] Read contents of memory into Read
MDR (using System Bus).
5 RF[Rt] <- MDR Transfer contents of MDR to Rt RFEN, RDorRT = 1, MDROE
register in RF.
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Questions?