Composite Date Types

 Arrays
– Single and multi-dimensional
– Single Type

 Records
– Mixed types

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Component

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 Component- Half Adder
library IEEE;
use IEEE.std_logic_1164.all;

entity xHA is
port( A, B: in std_logic;
SUM, CARRY: out std_logic);
end xHA;

architecture xHA_a of xHA is

begin
SUM <= A xor B;
CARRY <= A and B;
end xHA_a;
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 Component- Full Adder1

library IEEE;
use IEEE.std_logic_1164.all;

entity xFA is
port(
X,Y,Z : in std_logic;
SUMM : out std_logic;
COUT : out std_logic );
end xFA;

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 Component - Full Adder1

begin
architecture xFA_a of xFA is
ha1 : xha port map
component xha port
( A => X,
( A, B : in std_logic;
B => Y,
SUM : out std_logic;
SUM => S2,
CARRY : out std_logic);
CARRY=> S1 );
end component xha;
ha2 : xha port map
( A => S2,
signal S1,S2,S3 : std_logic;
B => Z,
SUM => SUMM,
CARRY=> S3 );
cout <= S1 OR S3;
end xFA_a;

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 Component - Full Adder2
library IEEE; architecture xxFA_a of xxFA is
use IEEE.std_logic_1164.all; component xha port
( A, B : in std_logic;
entity xxFA is SUM : out std_logic ;
port( X,Y,Z : in std_logic; CARRY : out std_logic);
SUMM :out std_logic; end component xha;
COUT : out std_logic);
end xxFA; signal S1,S2,S3 : std_logic;

begin
HA1 : xha port map(X, Y, S2, S1);
HA2 : xha port map(S2, Z, SUMM, S3);
cout <= S1 OR S3;
end xxFA_a;
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 Array

 Indexed Collection of Elements All of the

Same Type
– One-dimensional with one index
– Multi-dimensional with several indices

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 Array

– Constrained
» the bounds for an index are established when the
type is defined
– Unconstrained
» the bounds are established after the type is defined
– Each position in the array has a scalar index
value associated with it

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 Array Definition Syntax

array ( discrete_range { , ... } )

of element_subtype_indication ;

discrete_range is an index
– name of previously declared type with optional
range constraint

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 Array Declaration, e.g.,

type Large_Word is array ( 63 downto 0 )

of bit ;

type Address_List is array ( 0 to 7 ) of

Large_Word ;

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 Array Declaration, e.g.,
type 2D_FFT is array
( 1 to 128, 1 to 128 ) of real ;

type Scanner is array

( byte range 0 to 63 ) of integer ;

type Sensor_Status is array

( Stdby, On, Off ) of time ;

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 Array Declaration, e.g.,

subtype coeff_ram_address is
integer range 0 to 63;

type coeff_array is array

(coeff_ram_address) of real;

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 Array Example
architecture EXAMPLE of ARRAYS is
signal Z_BUS : bit_vector (3 downto 0);
signal C_BUS : bit_vector (0 to 3);
begin
Z_BUS <= C_BUS;
end EXAMPLE;

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 Array Example
architecture EXAMPLE of ASSIGNMENT is
signal Z_BUS : bit_vector (3 downto 0);
signal BIG_BUS : bit_vector (15 downto 0);
begin
-- legal assignments:
Z_BUS(3) <= ‘1’;
Z_BUS <= ”1100”;
Z_BUS <= b ”1100”;
Z_BUS <= x ”c”;
Z_BUS <= X ” C”;
BIG_BUS <= B ”0000 _ 0001_0010_0011”;
end EXAMPLE;
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 Array Example
architecture EXAMPLE_1 of CONCATENATION is
signal BYTE : bit_vector (7 downto 0);
signal A_BUS, B_BUS : bit_vector (3 downto 0);
begin
BYTE <= A_BUS & B_BUS;
end EXAMPLE;

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 Array Example
architecture EXAMPLE_2 of CONCATENATION is
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
begin
Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT;
end EXAMPLE;

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 Array Example
architecture EXAMPLE of AGGREGATES is
signal BYTE : bit_vector (7 downto 0);
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
begin
Z_BUS <= ( A_BIT, B_BIT, C_BIT, D_BIT ) ;
( A_BIT, B_BIT, C_BIT, D_BIT ) <= bit_vector(”1011”);
( A_BIT, B_BIT, C_BIT, D_BIT ) <= BYTE(3 downto 0);
BYTE <= ( 7 => ‘1’, 5 downto 1 => ‘1’, 6 => B_BIT, others => ‘0’) ;
end EXAMPLE;
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 Array Example
architecture EXAMPLE of SLICES is
signal BYTE : bit_vector (7 downto 0);
signal A_BUS: bit_vector (3 downto 0);
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT : bit;
begin
BYTE (5 downto 2) <= A_BUS;
BYTE (5 downto 0) <= A_BUS; -- Wrong

Z_BUS (1 downto 0) <= `0` & A_BIT;

Z_BUS <= BYTE (6 downto 3);
Z_BUS (0 to 1) <= `0` & B_BIT; -- Wrong
A_BIT <= A_BUS (0);
end EXAMPLE;

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 Memory Example
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity ram6116 is
port(address: in unsigned(7 downto 0);
data: inout std_logic_vector(7 downto 0);
WE_b, CS_b, OE_b: in std_ulogic);
end entity ram6116;

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 Memory Example
architecture simple_ram of ram6116 is
type ram_type is array (0 to 2**8-1) of std_logic_vector(7 downto 0);
signal ram1: ram_type:= (others => (others => ’0’));
begin
process
begin
data <= (others => ‘Z’); -- chip is not selected
if (CS_b = ‘0’) then
if rising_edge(WE_b) then -- write
ram1(conv_integer(address’delayed)) <= data;
wait for 0 ns;
end if;
if WE_b = ‘1’ and OE_b = ‘0’ then -- read
data <= ram1(conv_integer(address));
else
data <= (others => ‘Z’);
end if;
end if;
wait on WE_b, CS_b, OE_b, address;
end process; end simple_ram;

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 Memory Example (page 84)

entity coeff_ram is
port(rd, wr : in bit;
addr : in coeff_ram_address;
d_in : in real;
d_out : out real );
end entity coeff_ram;

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 Memory Example ..
architecture abstract of coeff_ram is
begin
memory: process is
type coeff_array is array (coeff_ram_address)
of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;

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 Memory Example ..
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;

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 Unconstrained Declaration
type Detector_Array is array
( natural range <> ) of natural ;
 The symbol ‘<>’ is called a box and can be
thought of as a place-holder for the index
range.
 Box is filled in later when the type is used.
variable X_Ray_Detector : Detector_Array
( 1 to 64 ) ;

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 Predefined Unconstrained Types

type string is array

( positive range <> ) of character ;

type bit_vector is array

( natural range <> ) of bit ;

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 Predefined Unconstrained Types

type std_ulogic_vector is array

( natural range <> ) of std_ulogic ;

type bit_vector is array

( natural range <> ) of bit ;

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 Unconstrained Array Ports

 Specify Port As Unconstrained

 Index Bounds of Signal Determine Size of

Port

 e.g., (Ashenden, P. 93), AND Gates With

Different Number of Inputs

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 Unconstrained Array Port, e.g.,

entity And_Multiple is

port ( i : in bit_vector ;
y : out bit ) ;

end entity And_Multiple ;

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 AND, e.g.,
architecture And_Multiple_B of And_Multiple is
begin
And_Reducer : process ( i ) is
variable Result : bit ;
begin
Result := ‘1’ ;
for Index in i’Range loop
Result := Result and i ( Index ) ;
end loop ;
y <= Result ;
end process And_Reducer ;
end architecture And_Multiple_B ;

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 AND, e.g.,

signal count_value :
bit_vector ( 7 downto 0 ) ;
signal terminal_count : bit ;
tc_gate : entity work.And_Multiple
( And_Multiple_B )
port map ( i => count_value ,
y => terminal_count ) ;

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 AND, e.g.,

 The Input Port Is Constrained by the Index

Range of the Input Signal, i.e., An 8-Input
AND Gate.

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 Array References
 Arrays Can Be Equated, Rather Than
Having to Transfer Element by Element
 Refer to Individual Elements By
– Single Index Value, e.g., A ( 5 )
– Range: a contiguous sequence of a one-
dimensional array can be referred to by using it
as an index. e.g., A( 5 to 15 )
– Previously defined subtype
– Index types do not have to be the same
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 Array Aggregate Syntax

 A List of Element Values Enclosed in

Parentheses
 Used to Initialize Elements of an Array to
Literal Values

aggregate <= ( [ choices => ]

expression { ... } )

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 Array Aggregate

 Two Ways of Referring to Elements

– Positional: explicitly list values in order
– Named Association: Explicitly list values by
their index using “choices”
» Order NOT important

 Positional and Named Association Cannot

Be Mixed Within an Aggregate.
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 Array Aggregate, e.g.,
type Sensor_Status is
array ( Stdby , On , Off ) of time ;

variable FLIR_Status :
Sensor_Status := ( 0 sec , 0 sec , 0 sec );

variable FLIR_Status :
Sensor_Status := ( On => 5 sec ) ;

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 Array Aggregate, e.g.,

 others Can Be Used in Place of an Index

in a Named Association, Indicating a Value
to Be Used for All Elements Not Explicitly
Mentioned

variable FLIR_Status : Sensor_Status :=

( Off => 10 min, others => 0 sec ) ;

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 Array Aggregate, e.g.,

 A Set of Values Can Be Set to a Single

Value by Forming a List of Elements
Separated by Vertical Bars, | .

type 2D_FFT is array

( 1 to 128, 1 to 128 ) of real ;
variable X_Ray_FFT : 2D_FFT :=
( ( 60, 68 ) | ( 62, 67 ) | ( 67, 73 )
| ( 60, 60 ) => 1.0 , others 0.0 ) ;
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 Array Operations
 One-Dimensional Arrays of Bit or Boolean
– Element by element AND, OR, NAND, NOR,
XOR, XNOR

type Large_Word is array

( 63 downto 0 ) of bit ;

variable Samp_1 , Samp_2 : Large_Word

( 0 to 63 => ‘0’ ) ;

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 Array Operations, e.g.,
constant Bit_Mask : Large_Word
( 8 to 15 => ‘1’ ) ;

Samp_2 := Samp_1 and Bit_Mask ;

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 Array Operations

– Complement of elements of a single array,

NOT

Samp_2 := not Samp_1 ;

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 Array Operations

 One-Dimensional Arrays Can Be Shifted

and Rotated
– Shift
» Logical: Shifts and fills with zeros
» Arithmetic: Shifts and fills with copies from the
end being vacated
– Rotate
» Shifts bits out and back in at other end

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 Array Operations, e.g.,

B” 1010_1100 ” sll 4 == B” 1100_0000 ”

B” 1010_1100 ” sla 4 == B” 1100_0000 ”

B” 1010_1101 ” sla 2 == B” 1011_0111 ”

B” 1010_1100 ” sra 4 == B” 1111_1010 ”

B” 1010_1100 ” rol 4 == B” 1100_1010 ”

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 Array Operations

 One-Dimensional Arrays Can Be Operated

on by Relational Operators,
= , /= , < , <= , > , >=
– Arrays need not be of the same length
– Arrays must be of same type

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 Array Operations

 Concatenation Operator, &

– Can combine array and scalar

B” 1010_1100 ” & B” 1100_0000 ” ==

B” 1010_1100_1100_0000 ”

B” 1010_1100 ” & ‘1’ == B” 1010_1100_1 ”

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 Array Type Conversions

 One Array Type Can Be Converted to

Another If:
– Same element type
– Same number of dimensions
– Same index types

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 Array Type Conversions, e.g.,

Ashenden Example

subtype name is string ( 1 to 20 ) ;

type display_string is array ( integer
range 0 to 19 ) of character ;
variable item_name : name ;
variable display : display_string ;
display := display_string ( item_name ) ;

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 Array Aggregate, e.g.,

 Assignments Can Be Made From a Vector

to an Aggregate of Scalars or Vice-Versa.

type Sensor_Status is array

( Stdby, On, Off ) of time ;

variable Stdby_Time, On_Time, Off_Time :

time ;

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 Array Aggregate, e.g.,
Variable FLIR_Status :
Sensor_Status := ( 0 sec ,
0 sec ,
0 sec ) ;

( Stdby_Time,
On_Time,
Off_Time ) := Flir_Status ;

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 Records

 Collections of Named Elements of Possibly

Different Types.

 To Refer to a Field of a Record Object, Use

a Selected Name.

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 Records

 Aggregates Can Be Used to Write Literal

Values for Records.

 Positional and Named Association Can Be

Used
– Record field names being used in place of array
index names.

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 Record e.g.,*
type instruction is
record
op_code : processor_op ;
address_mode : mode ;
operand1 : integer range 0 to 15 ;
operand2 : integer range 0 to 15 ;
end record ;

*Ashenden, VHDL cookbook

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End of Lecture

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