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Lecture 10 - Exception Handling

The Vectored Interrupt Controller (VIC) is a specialized hardware component that handles prioritized interrupts from multiple external sources for the ARM processor core, which only has two interrupt lines - IRQ and FIQ. The VIC takes in up to 32 interrupt requests, assigns them a priority level and designates them as either FIQ or IRQ. It then provides the address of the corresponding interrupt service routine to the processor core. This allows efficient handling of multiple concurrent interrupt sources.

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Suhaib Abugdera
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56 views

Lecture 10 - Exception Handling

The Vectored Interrupt Controller (VIC) is a specialized hardware component that handles prioritized interrupts from multiple external sources for the ARM processor core, which only has two interrupt lines - IRQ and FIQ. The VIC takes in up to 32 interrupt requests, assigns them a priority level and designates them as either FIQ or IRQ. It then provides the address of the corresponding interrupt service routine to the processor core. This allows efficient handling of multiple concurrent interrupt sources.

Uploaded by

Suhaib Abugdera
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Lecture 10

Exception Handling (continue)


Exercise
Vector Table
Abort
Undefined Instruction
Supervisor Mode(SVC)
Privileged Mode
Data Abort
FIQ
Interrupts
Prefetch Abort
Exceptions
IRQ
User mode/System mode
Exception Handlers
Example
00000014 ...
00000018 B irq_handler ;“Vector”
0000001C ...

irq_handler SUB lr, lr, #4 ;‘correct’ return addr.


STMFD SP!, {r0-r2,lr} ;Save working regs.
... ;code to handle the irq
...
... What is this??

LDMFD SP!, {r0-r2,pc}^ ;Restore and return


The caret (^)
• The caret (^) at the end of the instruction
forces the processor to transfer the SPSR into
the CPSR at the same time.
• Recommended way to exit an interrupt
handler
Restoring Program Counter (PC)
This instruction is used at the end of the handler
from a SWI or undefined instruction:
MOVS PC, R14
from an IRQ, FIQ or prefetch abort:
SUBS PC, R14, #4
from a data abort to retry the data access/transfer:
SUBS PC, R14, #8

‘S’ – When the destination register is PC (R15), ‘S’ flag serves


special function – restore CPSR from SPSR_xxx.
MOV instruction
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 I 1 1 0 1 S SBZ Rd shifter_operand

Writing to R15 (PC) [For example: MOVS R15, R0]


• If(S == 1) and (Rd == R15) and (in privilege mode)
– R15 = result
– CPSR  SPSR
– Flags are not affected

• If(S == 1) and (Rd == R15) and (in user mode/system mode)


– UNPREDICTABLE, there is no SPSR in user /system mode
– Do Not do this in user or system mode

• If(S == 1) and (Rd ≠ R15)


– Update CPSR’s N, Z, C flags
Switching Modes
• Processor mode can be changed by writing directly to
CPSR
– MSR CPSR_c, <source> ;Change processor mode

• Or by hardware when the processor responds to


exception or interrupt

• User mode is returned by using special instructions


– ‘S’ flag, with Rd == R15
– Caret (^)
Setting up Stack pointers
Stack pointers has to be properly set up for each
processor mode
• It is done every time the processor is reset
• Initialize SP by going through each mode
Vectored Interrupt Controller
Ch. 11.8.3.1 (Textbook)
Ch. 6 (LPC23xx user manual – UM10211)
What if…
The ARM processor core has only 2 interrupt lines:
 Interrupt ReQuest (IRQ)
 Fast Interrupt reQuest (FIQ)

• It works out well if there are only 2 I/O devices and/or peripheral units for
an entire system that need attention from the ARM core. However, this is
usually not the case!!!

• What if there are multiple ( > 2) sources (I/O devices or peripherals) that
can cause an interrupt to the ARM core?
Vectored IRQ
• Vectored IRQ’s, which include all interrupt requests that are
not classified as FIQs, have a programmable interrupt priority.

• When more than one interrupt is assigned the same priority


and occur simultaneously, the one connected to the lowest
numbered VIC channel (see Table 72 of UM10211) will be
serviced first.

• The VIC ORs the requests from all of the vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service
routine can start by reading a register from the VIC and
jumping to the address supplied by that register.
Vectored Interrupt Controller (VIC)
• VIC is a specialized hardware component

• VIC has multiple input lines and only 2 outputs


– FIQ output
– IRQ output

• VIC provides the address of the interrupt (exception)


handler

• More VIC information can be found at Chapter 6 of


the LPC23xx user manual (UM10211)
Vectored Interrupt Controller
• VIC is a memory-mapped device (addressable)

• It takes 32 interrupt request inputs and assigns them


as FIQ or IRQ types

• The VIC sends the address of each interrupt handler


to the processor core
Vectored Interrupt Controller (VIC)
• VIC is a specialized hardware component

• VIC has multiple input lines and only 2 outputs


– FIQ output
– IRQ output

• VIC provides the address of the interrupt (exception)


handler

• More VIC information can be found at Chapter 6 of


the LPC23xx user manual (UM10211)
Vectored Interrupt Controller (VIC)
• VIC is a specialized hardware component

• VIC has multiple input lines and only 2 outputs


– FIQ output
– IRQ output

• VIC provides the address of the interrupt (exception)


handler

• More VIC information can be found at Chapter 6 of


the LPC23xx user manual (UM10211)
FIQ
Fast Interrupt reQuest (FIQ) requests have the highest priority. If
more than one request is assigned to FIQ, the VIC ORs the
requests to produce the FIQ signal to the ARM processor.

The fastest possible FIQ latency is achieved when only one request
is classified as FIQ, because then the FIQ service routine can simply
start dealing with that device.
But if more than one request is assigned to the FIQ class, the FIQ
service routine can read a word from the VIC that identifies which
FIQ source(s) is (are) requesting an interrupt.
Vectored Interrupt Controller
• VIC is a memory-mapped device (addressable)

• It takes 32 interrupt request inputs and assigns them


as FIQ or IRQ types

• The VIC gives the address of each interrupt handler


to the processor core
Address and priority
• VICVectAddr0-31 registers are used to hold
the address of the interrupt service routine
(ISR)/interrupt handler for each one of 32
interrupt sources.

• VICVectPriority0-31 registers are used to set a


priority (0 – 15) of each one of 32 interrupt
sources.
VIC takes all interrupt inputs, assigning priorities to each of them, tells the
processor which component triggers an interrupt and where the interrupt
handler is located (in memory).

We, as programmers, configure the priorities, FIQ/IRQ classifications of the


interrupt sources.
Vectored Interrupt Controller
• VIC is a memory-mapped device (addressable)

• It takes 32 interrupt request inputs and assigns them


as FIQ or IRQ types

• The VIC gives the address of each interrupt handler


to the processor core
Source: ARM Architecture Reference Manual (UM10211 Rev4.1)
VIC registers map

The state of each interrupt request (32 possible


interrupts) can be read from Raw Interrupt Status
Register (VICRawIntr).
Vectored Interrupt Controller
• VIC is a memory-mapped device (addressable)

• It takes 32 interrupt request inputs and assigns


them as FIQ or IRQ types

• The VIC gives the address of each interrupt handler


to the processor core
FIQ or IRQ

Each one of 32 interrupts can be assigned as


either FIQ or IRQ using Interrupt Select Register
(VICIntSelect).

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