Lecture 1: Introduction
ECE323 - Introduction to Microprocessors
Topics
Microprocessor Organization
Organization of Microprocessor Systems
Endian-ness
ARM History and Characteristics
ARM7TDMI Implementation
LPC2378 Overview
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Microprocessor Components
Register file
Program counter
General purpose registers
Hidden registers
ALU
Buses
Memory interface
Control and timing unit
©2007 UW-Madison ECE323 – Introduction to Microprocessors 3
A Simple P Architecture
16
ADDR
TR0 PC AR
TEMPORARY REGISTER PROGRAM COUNTER ADDRESS REGISTER
8
DATA
Internal Data Bus
A IR
ACCUMULATOR TEMP REG GEN REG 0 R0 INST REG
GEN REG 1 R1
F GEN REG 2 R2
FLAGS
INSTRUCTION DECODER
/RD
ARITHMETIC AND LOGIC UNIT GEN REG 3 R3 TIMING AND CONTROL
(ALU) /WR
CLOCK
GENERATOR /RESET
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Instruction Set Architecture (ISA)
Complex Instruction Set (CISC)
Single instructions for complex tasks (string
search, block move, FFT, etc.)
Usually have variable length instructions
Registers have specialized functions
Reduced Instruction Set (RISC)
Instructions for simple operations only
Usually fixed length instructions
Large orthogonal register sets
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Basic ISA Classes
Stack
no register file but stack is used for operand(s)
Accumulator
One instruction operand comes from a dedicated register
(the accumulator) closely coupled to the ALU.
Register-Memory
Instruction operands can be obtained from both registers
and memory
Commonly used in CISC machines
Load-Store
All operands must be in general-purpose registers
Only a very limited number of instructions (loads/stores) can
“touch” memory
Commonly used in RISC machines
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Comparing ISA Classes
Code sequence for C = A + B for four classes
of instruction sets:
Stack Accumulator Register Register
(register-memory) (load-store)
Push A Load A Load R1, A Load R1, A
Push B Add B Add R1, B Load R2 ,B
Add Store C Store C, R1 Add R3, R1, R2
Pop C Store C, R3
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Microprocessor System Organization
Memory Architectures
Von Neumann architecture
Harvard architecture
Input/Output (I/O)
Memory-mapped I/O
Isolated I/O
Programmer’s Model
aka Register View
Memory Maps
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Register View of a Simple P
0000h
ACC
FLAGS
R0
R1
R2
R3
FFFFh
Regis ters Memory
aka “Von Neumann” or “Princeton”
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to Microprocessors 9
Register View of a Simple P
with Isolated I/O space
0000h 000h
ACC
FLAGS
R0
R1
R2 FFFh
R3 Isolated I/O
FFFFh
Regis ters Memory
Most microprocessors do NOT have– isolated
ECE323 I/O.
Introduction The Intel x86 microprocessors do.
to Microprocessors 10
Register View of a Simple P with
Separate Code and Data Memories
0000h
ACC
FLAGS
Program 000h
R0
FFFFh
R1
000h
R2
Data
R3
7FFh FFFh
Regis ters Memory Isolated I/O
(optional)
akaECE323
“Harvard” architecture
– Introduction to Microprocessors 11
Endian-ness
Byte Ordering for Little Endian vs. Big Endian
Byte Byte Byte Byte
0 1 2 3
Most Significant Least Significant
Byte (MSB) Byte (LSB)
Memory Address +0 +1 +2 +3
Big Endian Byte Byte Byte Byte MSB in the lowest (first)
0 1 2 3 memory address
Little Endian Byte Byte Byte Byte LSB in the lowest (first)
3 2 1 0 memory address
©2007 UW-Madison ECE323 – Introduction to Microprocessors 12
What is “ARM”?
A developing series of microprocessor
architectures
a 32-bit ‘RISC’ (Reduced Instruction Set
Computer)
initially quite simple in design
has evolved over ~25 years
no longer really “reduced”!
The company which develops it:
ARM Ltd, Cambridge, UK
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ARM Versions
Version 1
26 bit addressing, no multiply or coprocessor
Version 2
Includes 32-bit result multiply coprocessor
Version 3
32-bit addressing
Version 4
Add signed, unsigned half-word and signed byte load
and store instructions
Version 4T
16-bit Thump instructions
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ARM Versions
Version 5T
Superset of 4T adding new instruction
Version 5TE
Add signal processing extension
Examples:
ARM7TDMI : v4T
StrongARM: v4
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ARM Versions
In this course, we study ARM7TDMI
©2005 PEVEIT Unit ECE323 – Introduction to Microprocessors 16
The ARM7TDMI
The ARM7TDMI is...
an ARM7 3-stage pipeline core, with
T - support for the Thumb instruction set
D - support for debug
the processor can stop on a debug event
M - support for long multiplies
I - the EmbeddedICE macrocell
provides breakpoint and watchpoint hardware
described later
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ARM7TDMI
Processor
Core
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ARM performance
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ARM Size
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LPC2378
block
diagram
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Course Structure
This course covers both software and
hardware
Software – first
mainly architecture and instruction set
Hardware – second
– primarily the programmer’s view
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Course Structure - Software
The ARM software development toolkit
exploring the toolkit
ARM7 assembly language programming
writing simple assembly programs
Support for high-level languages
C programs and debugging
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Course Structure - Hardware
The ARM7 Architecture
Parallel Input & Output
Keypad & LCD
Interrupt
Memory
Serial communication
A/D conversion
Timer
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Toolkit introduction
Outline:
the ARM programmers’ model
the ARM software development tools
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The ARM programmers’ model
ARM is a Reduced Instruction Set Computer
(RISC); it has:
a large, regular register file
any register can be used for any purpose
a load-store architecture
instructions which reference memory just move data,
they do no processing
processing uses values in registers only
fixed-length 32-bit instructions
good speed/power consumption ratio
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Enhancement to Basic RISC Features
Ability to implement shift and ALU operation
in a single cycle
Auto-increment and auto-decrement
addressing modes to optimize program loops
Load and store multiple instructions
Conditional execution
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ARM register organization
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The ARM programmers’ model
The user has sixteen 32-bit registers (r0-r15)
all register operations are 32-bit
r13: stack pointer
r14: link register
r15 acts as the program counter (a.k.a. “PC”)
memory transfers may be smaller but loads always
extend
A current program status register (CPSR)
holds some extra bits
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ARM CPSR format
In user programs only the top 4 bits of the
CPSR are significant:
N - the result was negative
Z - the result was zero
C - the result produced a carry out
V - the result generated an arithmetic overflow
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ARM memory organization
Memory is a linear
array of 232 byte
locations.
ARM can address:
individual bytes
32-bit words on 4-byte
boundaries
16-bit half-words on 2-
byte boundaries
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ARM Developer Suite
We will use Keil Software development tools called uVision4
Evaluation version is free and available at :
[Link]
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uVision
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MCB2300 Evaluation Board
We will use MCB2300 Evaluation Board populated with
an LPC2378 microcontroller, which has ARM7 core.
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MCB2300 & Breadboard
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