Advanced IC Technology

UNIT-5
Manufacturing process of MOS Devices
oMOS field effect transistor is widely used particularly in digital logic circuits and as memory
devices. This is because, we need very high packing density for the memory.
o It means when we need high packaging density we will use MOSFET’S (the entire area of
MOSFET is less than 5% of the area required for the BJT) otherwise if we need high speed we
will chose BJT’s.
o There are a large number and variety of basic fabrication steps used in the production of modern
MOS ICs.
 F SYSTEM DI
O GI
TA

ble
LD
Cell-Based

Se
FPGA

ma

mi
Co
L

ram

-C
OR
or ntr

us
s PLD Gate oll
IC
s

og

to
ro ce ASIC er

Pr
Arrays

m
p Ch
W
o ip
Mi
cr
ose Full-Custom
urp AS
ral
P MODULE Mo
SP
e
en A M de

DECODER
m
G SR Ch
M
& Combinational Sequential ip
A
DR R
E
X G
LOGIC GATE

M
 Dynamic

EM
A
Static D Q M

OR
U B
Ci

Y
Basic X
FA

CIRCUIT Co
S

Simple Complex
Parallel Series
Connection CMOS Inverter Connection

DEVICE n p
n+ p n+ n+ n+
p
Bipolar Diode
MOSFET
Classification of MOSFET
◦ Enhancement MOSFET : are devices which off at zero gate–source
voltage, and can be turned on by pulling the gate voltage either higher
than the source voltage, for NMOS, or lower than the source voltage for
PMOS.
◦ Depletion MOSFET: is the device which is normally ON at zero gate–
source voltage (there is a pre existing channel).
◦ MOSFET can be also classified into two; PMOS and NMOS.
MOSFET Types and Symbols
D D D I DS D I DS

G G G B G

S S S 0 +V VGS S -VTn VGS

With non standard Tn 0
Analog Digital
substrate connection

Enhancement NMOS Depletion NMOS

D D D VGS -V Tp VGS 0 +V
0 D Tp

G G G B G

S S S
S
Analog Digital
With non standard I DS I DS
substrate connection

Enhancement PMOS Depletion PMOS

Enhancement mode transistors are normally OFF (non-conducting with zero

bias)
Depletion mode transistors are normally ON (conduct with zero bias)
Most CMOS ICs use Enhancement type MOS
Comparison of BJT with MOSFET
MOSFET is smaller in size and easier to fabricate than BJT.
MOSFET is less noisy than BJT.
BJT is noisy device [because of minority carrier], in BJT there is a minority carrier storage time.
But in MOSFET minority carrier storage time is zero and therefore switching times are smaller.
MOSFET is faster than BJT.
When compared to BJT, MOSFET is relatively more suitable for high frequency applications.
MOSFET has low voltage gain, high current gain, very high input impedance, high out put
impedance and easily damaged by static. But BJT has high voltage gain , low current gain, low
input impedance, low output impedance and it is robust.
Comparison of NMOS and PMOS
 NMOS is faster than PMOS, because of μn > μp.
 PMOS is easier to fabricate.
 NMOS suffers from ion contamination problem during the fabrication.
 In PMOS ion contamination problem is very less
 PMOS is cheaper and also bulky.
 To get equal performance between NMOS and PMOS; PMOS requires twice the area
required for NMOS.
 The main advantage of NMOS is higher package density that is it can store large amount of
performance in the smaller area.
nMOS Fabrication process
The process starts with production of the substrate. The substrate is of p type single crystal
silicon wafer.
The first step is to grow a thick silicon dioxide (SiO2) layer, typically of 1μm thickness all over
the wafer surface using the wet oxidation technique.

Thick SiO2 (1 μm)

Continue…
The surface is now covered with a photo resist
which is deposited onto the wafer and spun to
achieve an even distribution of the required
thickness.
The photo resist layer is then exposed to ultraviolet
light through a mask which defines those regions
into which diffusion is to take place together with
transistor channels. Assume, for example, that those
areas exposed to ultraviolet radiation are
polymerized (hardened), but that the areas required
for diffusion are shielded by the mask and remain
unaffected
Continue…
These areas are subsequently readily etched away together
with the underlying silicon dioxide so that the wafer surface
is exposed in the window defined by the mask.
The remaining photoresist is removed and a thin layer of
Si02 is grown over the entire chip surface and then
polysilicon is deposited on top of this to form the gate
structure.
Continue…
Further photo resist coating and masking allows the polysilicon
to be patterned (as shown in Step 6 and 7) and then the thin
oxide is removed to expose areas into which n- type impurities
are to be diffused to form the source and drain as shown.
Thick oxide (Si02) is grown over all again and is then masked with
photoresist and etched to expose selected arcs of the polysilicon
gate and the drain and source areas where connections (i.e.
contact cuts) are to be made.
Continue…
Thick oxide (Si02) is grown over all again and is then masked with
photoresist and etched to expose selected arcs of the polysilicon gate
and the drain and source areas where connections (i.e. contact cuts)
are to be made.
The whole chip then has metal (aluminium) deposited over its
surface to a thickness typically of 1μm. This metal layer is then
masked and etched to form the required interconnection pattern.
Threshold voltage
One of an important parameter of MOSFET is threshold voltage of the device. The threshold voltage of
MOSFET device depends on the following main factors:
◦ On gate oxide thickness

◦ On the substrate doping concentration

◦ On what kind of metal we used on the gate

These things are to some extent in our control. But, there are certain things which are not in our control
process related things which are very difficult to control and these are unwanted charges in the oxides
Ideally speaking the gate oxide should be a dielectric. But during the oxidation of silicon these are
possibility that are some charge will be introduced in the oxide it may be due to:
◦ Incomplete oxidation

◦ Presence of mobile ions like Sodium, Potassium.

Continue…
So now a days, it is a common practice; it is in fact one common step in MOSFET fabrication to have
what is known as a threshold tailoring implant.
This implantation is done only in the channel region of the MOSFET; no where else, only in the
channel region of the MOSFET very close to the surface, just in order to tailor threshold voltage, so
that you can realize the threshold voltage of your choice.
This would not have been possible with the other less sophisticated doping techniques like diffusion.
It is possible with ion implantation. So, that brings us to our processing step that is ion implantation.
Even though, it looks on the face of it that the MOSFET technology is simpler, it is in fact not so. It is
true that you need lesser number of steps, but these steps have to be more carefully controlled .
Cmos fabrication process
Complementary metal–oxide semiconductor (CMOS) is a technology that is used for making low
power integrated circuits. Has many different uses:
◦ Data converters
◦ Image sensors Logic circuits
◦ Microprocessors
◦ Microcontrollers
◦ Static RAM

CMOS can be fabricated using different process such as: N-well process P-well process
Continue…
Step 1: Si Substrate Primarily, start the process with a P-substrate.
Step 2: Oxidation The oxidation process is done by using high-purity oxygen and hydrogen, which are
exposed in an oxidation furnace approximately at 1000 degree.
Step 3: Photoresist Coating A light-sensitive polymer that softens whenever exposed to light is called as
Photoresist layer. It is formed.
Step 4: Masking Expose photoresist to UV rays through n-well.
Step 5: Removal of Photoresist Photoresist are removed by treating the wafer with acidic or basic
solution.
Step 6: Removal of SiO2 using acid etching SiO2 is selectively removed from areas of wafer that are not
covered by photoresist by using hydrofluoric acid.
Step 7: Removal of Photoresist The entire photoresist layer is stripped off, as shown in the below figure.
Step 8: Formation of n-well By using ion implantation or diffusion process N-well is formed. 
Continue…
Step 9: Removal of SiO2 Using the hydrofluoric acid,
the remaining SiO2 is removed.
SiO2
Step 10: Polysilicon deposition Deposit very thin layer
of gate oxide using Chemical Vapour Deposition (CVD)
process n well

Step 11: Removing the layer barring a small area for

the Gates Except the two small regions required for
forming the Gates of NMOS and PMOS, the remaining
layer is stripped off. n well
p substrate
Step12: Oxidation process Next, an oxidation layer is
formed on this layer with two small regions for the
formation of the gate terminals of NMOS and PMOS.
p+ n+ n+ p+ p+ n+

Step13: Masking and N-diffusion By using the masking p substrate

n well

process small gaps are made for the purpose of N-

diffusion. The n-type (n+) dopants are diffused or ion
implanted, and the three n+ are formed for the
formation of the terminals of NMOS.
Continue…
Step14: Oxide stripping The remaining oxidation layer is
stripped off.
Step15: P-diffusion Similar to the above N-diffusion process, p+ n+ n+ p+ p+ n+
the P-diffusion regions are diffused to form the terminals of n well
the PMOS. p substrate

Step16: Thick field oxide A thick-field oxide is formed in all

regions except the terminals of the PMOS and NMOS.
Metal
Step 17: Metallization Aluminum is sputtered on the whole Thick field oxi
wafer. Pattern to remove excess metal, leaving wires p+ n+ n+ p+ p+ n+

Step18: Removal of excess metal The excess metal is n well

p substrate
removed from the wafer layer.
Step19: Terminals The terminals of the PMOS and NMOS are
made from respective gaps.
Step20: Assigning the names of the terminals of the NMOS
and PMOS Where, Gate (G),Body (B), Source (S) and Drain
(D) terminals.
Final CMOS
Fabrication of CMOS using P-well process
Among all the fabrication processes of the CMOS, N-well process is mostly used for the
fabrication of the CMOS.
P-well process is almost similar to the N-well. But the only difference in p-well process is that
it consists of a main N-substrate and, thus, P-well acts as substrate for the N-devices.
For simplicity usually, N well process is preferred.
Twin Tube Fabrication of CMOS
Using Twin-tube process one can control the gain of P and N-type devices.
A lightly doped n or p-type substrate is taken and the epitaxial layer is used. Epitaxial layer
protects the latch-up problem in the chip.
The high purity silicon layers with measured thickness and exact dopant concentration are
grown.
Formation of tubes for P and N well.
Thin oxide construction for protection from contamination during diffusion processes.
Source and drain are formed using ion implantation methods.
Cuts are made for making portions for metal contacts.
Metallization is done for drawing metal contacts
CMOS IC Layout

Twin Tube CMOS