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Computer System Organization

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Shazia Munir
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31 views

Computer System Organization

Uploaded by

Shazia Munir
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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COMPUTER SYSTEM

ORGANIZATION
GROUP MEMBERS:
SHAZIA MUNEER
TAIMIYA ZAHRA
SHANZA JAMEEL
TASKEEN ZAHRA
PERIPHERAL COMPONENTS INTERCONNECT (PCI)

 Generally, PCI express refers to the actual expansion slots on the motherboard that accept PCIe-
based expansion cards and to the types of expansion cards themselves.
 PCI express has all but replaced Accelerated Graphics Port (AGP) and Peripheral Components
Interconnect (PCI), both of which replaced the oldest widely-used connection type called Industry
Standard Architecture (ISA).
NEED FOR PCI EXPRESS

 Applications, such as streaming video and photo editing, put heavy demands on pcs to move vast
amounts of data ever quicker.
 As processor clock speeds increase, parallel buses such as PCI become harder to implement.
Signal skew and fan-out restrictions restrict the bandwidth achievable on a parallel bus.
 The solution is a bus architecture that uses both parallel and serial transfers. It’s called PCI-
express, or PCI-E.
 Pci express (PCIe) has arisen to break the bandwidth barrier while maintaining software
compatibility with the popular PCI bus.
HOW PCI-EXPRESS BREAKS THE BUS BARRIER

 PCI express (PCIe) has arisen to break the bandwidth barrier while maintaining software


compatibility with the popular PCI bus. The problem that PCIe aims to solve is the inability of
conventional parallel buses to scale to today's processor speeds.
• A PCI-express bus breaks all data it handles into pieces and wraps the pieces in a packet. The
packet includes other binary codes that identify where the information has come from, where it's
headed, its sequence among all the other packets being sent, and the results of a cyclic
redundancy check (CRC). A CRC is a mathematical operation that acts as fingerprint for the data.
 As with the older PCI bus, the two components in the motherboard's chip set work together to shepherd
data among peripherals. The part of the chip set referred to as the north bridge continues to be the chip
that rushes packets to the CPU and RAM, the components for which speed is most critical. It has
traditionally passed less urgent packets to the south bridge for handling.
 In a PCI-express bus, the south bridge continues its relatively unheroic job of dribbling data to the
pokey hard drives, USB connections, and legacy PCI cards. But now the south bridge feeds packets to
components, such as video cards, that are data speed freaks. It does so by using dedicated serial circuits
for each component, simultaneous back-and-forth transmission, and parallel routes for its serial signals.
 The chip set sends packets serially over two lines. Another pair of lines is responsible for packets
going in the opposite directions. Taken together, the two pairs are called a lane. One of the lines
in each pair carries the original signal. The other line carries a negative image of the signal; each
o becomes a 1 and each 1 becomes a 0. The lines are laid out so that any electrical noise, or
static, that affects one line should also affect the other.
 When packets reach their destination, the receiver restores
the negative packet to its positive version. That same
operation reverses the values of any junk signals
introduced by electrical interference. The bus combines
the two paired packets, and any interference in the
original packet is canceled by its negative image in the
matching packet.
 It also performs the same CRC operation that was
performed on the packet before its journey and compares
its result to the earlier one bundled into the packet. If
CRCs differ, the bus orders the packet be re-sent. Because
the sequence of the data in each packet is included in the
packet, the bus doesn't have to wait for the corrected
packet. It can continue to accept other packets and
shoehorn the corrected data into its proper place in line
when it arrives.
 After subtracting the overhead for packet packaging, the basic PCI-express slot has a top bandwidth
of 250 megabytes a second. But PCI-E is scalable. Devoting two or more lanes to send data to and
from a single component-called channel bonding-increases the bandwidth for each lane added to
the channel. PCI-E transfers data at 250MB a second in each direction per lane. With a maximum
of 32 lanes, PCI-E allows for a total combined transfer rate of 8GB a second in each direction. That
gives a single channel nearly twice the bandwidth of the older PCI and an eight lane slot a data rate
comparable to the fastest version of AGP. You can identify the expansion slots with the increased
bandwidth by comparing the slots' lengths. The basic PCI-E slot is about 24.5mm long. Each
13.5mm added to other slots represents another 250MB added to their bandwidth.
• In the older PCI bus, all the devices share the same parallel circuits and receive the same data.
The data includes an identifier that says which device the signals are destined for. All other
devices simply ignore them. But like telephone users on a party line, the components can't
receive data while some other device monopolizes the connection. The links in PCI-E are point-
to-point. The south bridge uses a crossbar switch to route incoming signals from one point to
another down circuit lines dedicated to specific components. Data goes to several components at
the same time. It's like talking on a private, single-line phone.
DEVELOPING WITH PCIE

 Numerous devices using the PCIe interface-have become available, as have silicon cores for
custom designs. Designers interested in using devices should ensure that the offerings have been
certified to PCISIG specifications.
 Developers seeking controller cores for custom devices should check if the core has been used in
a device that has passed compliance testing. For PHY cores, look for expertise in high-speed
board design. In both cases, the more software and design support the vendor offers, the easier it
will be to use pcie to break the bandwidth bottleneck of PCI-based systems.
THE END!

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