Integrated

Circuits
A Design
Perspective
Dr. J. Raja Paul Perinbam
Dept. of ECE
Anna University

Basic Circuits for

Digital Systems

Digital Integrated Circuits2nd Inverter

 CMOS
Inverter

Digital Integrated Circuits2nd Inverter

 The CMOS Inverter: A
First Glance
V DD

V in V out

CL

Digital Integrated Circuits2nd Inverter

 CMOS Inverter
N Well VDD

VDD PMOS 2λ

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

Digital Integrated Circuits2nd Inverter

 Two Inverters
Share power and ground

Abut cells

VDD
Connect in Metal

Digital Integrated Circuits2nd Inverter

 CMOS Inverter
First-Order DC Analysis
V DD V DD

Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out

Rn

V in 5 V DD V in 5 0

Digital Integrated Circuits2nd Inverter

 CMOS Inverter: Transient
Response
V DD V DD

Rp tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout
CL CL
Rn

Vin 5 0 Vin 5 V DD
(a) Low-to-high (b) High-to-low

Digital Integrated Circuits2nd Inverter

 Voltage
Transfer
Characteris
tic

Digital Integrated Circuits2nd Inverter

 PMOS Load Lines

IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp

Vout

IDp IDn IDn

Vin=0 Vin=0

Vin=1.5 Vin=1.5

V DSp VDSp Vout

VGSp=-1

VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

Digital Integrated Circuits2nd Inverter

 CMOS Inverter Load
Characteristics

ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout

Digital Integrated Circuits2nd Inverter

 CMOS Inverter VTC

Vout NMOS off

2.5 PMOS res
NMOS s at
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0 .5 1 1 .5 2 2 .5 Vin
Digital Integrated Circuits2nd Inverter
 Determining VIH and VIL
Vout

V OH

VM

V in
V OL
V IL V IH

A simplified approach

Digital Integrated Circuits2nd Inverter

 Inverter Gain
0

­2

­4

­6

­8
g a in

­1 0

­1 2

­1 4

­1 6

­1 8
0 0 .5 1 1 .5 2 2 .5

V   (V )
in

Digital Integrated Circuits2nd Inverter

 Gain as a function of
VDD
2 .5 0 .2

2
0 .1 5

1 .5

  (V )
(V )

0 .1

out
out

V
V

0 .0 5

0 .5

Gain=-1
0
0 0 0 .0 5 0 .1 0 .1 5 0 .2
0 0 .5 1 1 .5 2 2 .5
V  (V )
V   (V ) in
in

Digital Integrated Circuits2nd Inverter

 Propagation
Delay

Digital Integrated Circuits2nd Inverter

 Delay
Approach 1
VDD

tpHL = CL Vswing/2
Iav

Vout CL
~
Iav CL kn VDD

Vin = V DD

Digital Integrated Circuits2nd Inverter

 CMOS Inverter Propagation
Delay
Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
Ron
1 VDD

0.5
0.36

Vin = V DD
t
RonCL

Digital Integrated Circuits2nd Inverter

 CMOS Inverters
VDD

PMOS

1.2µm
=2λ
Out
In
Metal1

Polysilicon

NMOS
GND

Digital Integrated Circuits2nd Inverter

 Transient Response
3

2 .5
?
2

tp = 0.69 CL (Reqn+Reqp)/2
1 .5
(V )
out

1 tpLH tpHL
V

0 .5

­0 . 5
0 0 .5 1 1 .5 2 2 .5
t   (s e c ) ­10
x  1 0

Digital Integrated Circuits2nd Inverter

 Delay as a function of VDD
5 .5

4 .5

4
t (n o rm a liz e d )

3 .5

3
p

2 .5

1 .5

1
0 .8 1 1 .2 1 .4 1 .6 1 .8 2 2 .2 2 .4

V (V )
D D

Digital Integrated Circuits2nd Inverter

 Impact of Rise Time on
Delay
0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

Digital Integrated Circuits2nd Inverter

 Inverter
Sizing

Digital Integrated Circuits2nd Inverter

 Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

Digital Integrated Circuits2nd Inverter

 Inverter Delay
• Minimum length devices, L=0.25µm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays W
• Analyze as an RC network
−1 −1
 WP   WN 
RP = Runit   ≈ Runit   = RN = RW
 Wunit   Wunit 

Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL

W
Load for the next stage: C gin =3 Cunit
Wunit
Digital Integrated Circuits2nd Inverter
 Inverter with Load
Delay

RW

CL
RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
Digital Integrated Circuits2nd Inverter
 Inverter with Load
CP = 2Cunit Delay

2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

Digital Integrated Circuits2nd Inverter

 Delay Formula

Delay ~ RW ( Cint + C L )

t p = kRW Cint (1 + C L / Cint ) = t p 0 (1 + f / γ )

Cint = γCgin with γ ≈ 1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
Digital Integrated Circuits2nd Inverter
 Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin , j +1 
t pj ~ Runit Cunit 1 + 
 γC 
 gin , j 
N N  C gin , j +1 
t p = ∑ t p , j = t p 0 ∑ 1 + , C gin , N +1 = C L
 γC
i =1 

j =1 gin , j 

Digital Integrated Circuits2nd Inverter

 Optimum Delay and
Number of Stages
When each stage is sized by f and has same eff. fanout f:
f N
= F = C L / C gin ,1

Effective fanout of each stage:

f =NF
Minimum path delay

(
t p = Nt p 0 1 + N F / γ )
Digital Integrated Circuits2nd Inverter
 Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f =38 =2

Digital Integrated Circuits2nd Inverter

 Optimum Number of
Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L = F ⋅ Cin = f Cin with N =
N

ln f
t p 0 ln F  f γ 
( 1/ N
)
t p = Nt p 0 F / γ + 1 =  +
γ  ln f ln f


∂t p t p 0 ln F ln f − 1 − γ f
= ⋅ =0
∂f γ ln f 2

For γ = 0, f = e, N = lnF f = exp(1 + γ f )

Digital Integrated Circuits2nd Inverter
 Optimum Effective
Fanout f
Optimum f for given process defined by γ
f = exp(1 + γ f )
fopt = 3.6
for γ=1

Digital Integrated Circuits2nd Inverter

 Buffer Design
N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

Digital Integrated Circuits2nd Inverter

 Power
Dissipation

Digital Integrated Circuits2nd Inverter

 Where Does Power Go in
CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

Digital Integrated Circuits2nd Inverter

 Dynamic Power
Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

Digital Integrated Circuits2nd Inverter

 Modification for Circuits with Reduced Swing
Vdd
Vdd

Vdd ­Vt

CL

E 0 → 1 = CL • Vdd • ( V dd – Vt )

Can exploit reduced swing to lower power
(e.g., reduced bit­line swing in memory)

Digital Integrated Circuits2nd Inverter

 Static Power Consumption
Vdd

Istat
Vout

CL
Vin =5V

Pstat = P(In=1).Vdd . Istat

Wasted• Dominates over dynamic consumption
energy …
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)

Digital Integrated Circuits2nd Inverter

 Principles for Power
Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47

Digital Integrated Circuits2nd Inverter

 Impact of
Technology
Scaling

Digital Integrated Circuits2nd Inverter

 Technology Scaling
 Goals of scaling the dimensions by 30%:
 Reduce gate delay by 30% (increase operating
frequency by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
 Die size used to increase by 14% per
generation
 Technology generation spans 2-3 years

Digital Integrated Circuits2nd Inverter

 Technology Scaling
Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors

Digital Integrated Circuits2nd Inverter

 Design
Layout
Rules

Digital Integrated Circuits2nd Inverter

 CMOS Process

Digital Integrated Circuits2nd Inverter

 A Modern CMOS
Process
gate-oxide

TiSi2 AlCu

SiO2
Tungsten

poly
p-well n-well SiO2
n+ p-epi p+

p+

Dual-Well Trench-Isolated CMOS Process

Digital Integrated Circuits2nd Inverter

 Circuit Under Design
VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

Digital Integrated Circuits2nd Inverter

 Its Layout View

Digital Integrated Circuits2nd Inverter

 3D Perspective

Polysilicon Aluminum

Digital Integrated Circuits2nd Inverter

 Design Rules

 Interface between designer and process

engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width

 scalable design rules: lambda parameter

 absolute dimensions (micron rules)

Digital Integrated Circuits2nd Inverter

 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

Digital Integrated Circuits2nd Inverter

 Layers in 0.25 µ m
CMOS process

Digital Integrated Circuits2nd Inverter

 Intra-Layer Design
Rules
Same Potential Different Potential

9 2
0 
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Metal2
Select

Digital Integrated Circuits2nd Inverter

 Transistor Layout
Transistor

3 2

Digital Integrated Circuits2nd Inverter

 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to Poly Contact
1
Active Contact 3 2

2
2

Digital Integrated Circuits2nd Inverter

 Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate

Digital Integrated Circuits2nd Inverter

 CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p­substrate Field
+ +
n p Oxide
(b) Cross­Section along A­A’

Digital Integrated Circuits2nd Inverter

 Layout Editor

Digital Integrated Circuits2nd Inverter

 Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Digital Integrated Circuits2nd Inverter

 Sticks Diagram
V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

Digital Integrated Circuits2nd Inverter

 Construction
of
multiplexers,
transmission
gates,
latches, flip-
flops

Digital Integrated Circuits2nd Inverter

 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK

2 storage mechanisms
• positive feedback
• charge-based

Digital Integrated Circuits2nd Inverter

 Latch versus Register
 Latch  Register
stores data when stores data when
clock is low clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

Digital Integrated Circuits2nd Inverter

 Latches
Positive Latch Negative Latch

In D Q Out In D Q Out
G G

CLK CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

Digital Integrated Circuits2nd Inverter

 Latch-Based Design
• N latch is transparent • P latch is transparent
when φ = 0 when φ = 1
φ

N P
Logic
Latch Latch

Logic

Digital Integrated Circuits2nd Inverter

 Timing Definitions

CLK
t Register
tsu thold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

Digital Integrated Circuits2nd Inverter

 Positive Feedback: Bi-
Stability
V i1 V o1 =V i2 V o2

Vo1 Vi2
V o2 =V i 1

Vi1 Vo2

A
Vi2 =Vo1

B
Vi1 =Vo2

Digital Integrated Circuits2nd Inverter

 Meta-Stability
A A
V i2 5 V o1

V i2 5 V o1
C C

B B
V i1 5 V o2 V i1 5 V o2
d d
Gain should be larger than 1 in the transition region

Digital Integrated Circuits2nd Inverter

 Writing into a Static
Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK

Q D D
CLK
CLK
D

CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)

Digital Integrated Circuits2nd Inverter

 Mux-Based Latches
Negative latch Positive latch
(transparent when CLK= 0) (transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK CLK

Q = Clk ⋅ Q + Clk ⋅ In Q = Clk ⋅ Q + Clk ⋅ In

Digital Integrated Circuits2nd Inverter

 Mux-Based Latch
CLK

CLK

CLK

Digital Integrated Circuits2nd Inverter

 Mux-Based Latch

CLK
QM
CLK

QM

CLK

CLK

NMOS only Non-overlapping clocks

Digital Integrated Circuits2nd Inverter

 Master-Slave (Edge-
Triggered) Register
Slave
Master

0 Q D
1 QM
1
QM
D 0 Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

Digital Integrated Circuits2nd Inverter

 Master-Slave Register

Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

Digital Integrated Circuits2nd Inverter

 Clk-Q Delay

2.5
CLK

1.5
Volts

D
tc 2 q(lh) tc 2 q(hl)
Q
0.5

2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

Digital Integrated Circuits2nd Inverter

 Other Latches/Registers:
C MOS
2

VDD VDD

M2 M6

CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7

M1 M5

Master Stage

“Keepers” can be added to make circuit pseudo-static

Digital Integrated Circuits2nd Inverter

 Timing and

Fan-out
considerati
ons

Digital Integrated Circuits2nd Inverter

 Latch Parameters

D Q

Clk

T
Clk PWm
tsu
D
thold

tc-q td-q
Q

Delays can be different for rising and falling data transitions

Digital Integrated Circuits2nd Inverter
 Register Parameters

D Q

Clk

T
Clk

D thold

tsu
tc-q
Q

Delays can be different for rising and falling data transitions

Digital Integrated Circuits2nd Inverter
 Clock Uncertainties
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices

7 Coupling to Adjacent Lines

5 Temperature
1 Clock Generation

Sources of clock uncertainty

Digital Integrated Circuits2nd Inverter

 Clock Nonidealities
 Clock skew
 Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
 Clock jitter
 Temporal variations in consecutive edges of the
clock signal; modulation + random noise
 Cycle-to-cycle (short-term) tJS
 Long term tJL
 Variation of the pulse width
 Important for level sensitive clocking

Digital Integrated Circuits2nd Inverter

 Clock Skew and Jitter
Clk
tSK

Clk tJS

 Both skew and jitter affect the effective cycle time

 Only skew affects the race margin

Digital Integrated Circuits2nd Inverter

 Clock Skew
# of registers

Earliest occurrence Latest occurrence

of Clk edge of Clk edge
Nominal – δ /2 Nominal + δ /2

Insertion delay Clk delay

Max Clk skew

Digital Integrated Circuits2nd Inverter

 Positive and Negative
Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
(a) Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay
(b) Negative skew

Digital Integrated Circuits2nd Inverter

 Positive Skew

TCLK  
TCLK
1
CLK1


CLK2 2 4
  th

Launching edge arrives before the receiving edge

Digital Integrated Circuits2nd Inverter

 Negative Skew

TCLK + 
TCLK
1 3
CLK1

CLK2 2 4


Receiving edge arrives before the launching edge

Digital Integrated Circuits2nd Inverter

 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc  q tlogic
tc  q, cd t
tsu, thold

Minimum cycle time:

T - δ = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive δ)

Digital Integrated Circuits2nd Inverter

 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc  q tlogic
tc  q, cd t
tsu, thold

Hold time constraint:

t(c-q, cd) + t(logic, cd) > thold + δ
Worst case is when receiving edge arrives late
Race between data and clock

Digital Integrated Circuits2nd Inverter

 Impact of Jitter
 TC LK 
  t j itter
CLK 
-tji tte r 

REGS Combinational
In Logic

CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter

Digital Integrated Circuits2nd Inverter

 Flip-Flop – Based
Timing
Skew Flip-flop
Logic delay delay
φ

TSU
Flip TClk-Q
-flop
φ=1
φ=0
Logic

Representation after
M. Horowitz, VLSI Circuits 1996.

Digital Integrated Circuits2nd Inverter

 Flip-Flops and Dynamic
Logic
Logic delay

TSU
TSU TClk-Q
TClk-Q
φ=1
φ=1 φ=0
φ=0

Logic delay
Precharge Evaluate Precharge
Evaluate

Flip-flops are used only with static logic

Digital Integrated Circuits2nd Inverter

 Latch timing
tD-Q When data arrives
to transparent latch
Latch is a ‘soft’ barrier
D Q

Clk

tClk-Q When data arrives

to closed latch

Data has to be ‘re-launched’

Digital Integrated Circuits2nd Inverter

 Single-Phase Clock with
Latches
φ

Latch

Logic

Tskl Tskl Tskt Tskt

Clk
PW
P

Digital Integrated Circuits2nd Inverter

 Latch-Based Design
L1 latch is L2 latch is transparent
transparent when φ = 1
φ
when φ = 0

L1 L2
Logic
Latch Latch

Logic

Digital Integrated Circuits2nd Inverter

 Latch-Based Timing
Skew
Static logic
φ

L2 latch
L1
Logic
L2 φ=1
Latch Latch

L1 latch

Logic
Long φ=0
path

Can tolerate skew!

Short
path

Digital Integrated Circuits2nd Inverter

 Fan-in and Fan-out

M
N

Fan-out N Fan-in M

Digital Integrated Circuits2nd Inverter

 The Ideal Gate
V out

Ri = ∞
Ro = 0
Fanout = ∞
g=∞
NMH = NML = VDD/2

V in

Digital Integrated Circuits2nd Inverter

 Thank
you !

Digital Integrated Circuits2nd Inverter