COMPUTER

INSTRUCTION SET

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Outline
 Instruction

 Op-Code Encoding

 Encoding Techniques
 Block-Code Technique
 Expanding Op-Code Technique
 Huffman Encoding

 Addressing Modes

 Instruction Types

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An instruction manipulates the stored data, and a sequence of instructions
constitutes a program. In general, an instruction has two components:

 Op-Code field

 Operand/Address Field (s)

The Op-Code field specifies how data is to be manipulated. The data items may
reside within a CPU register or in the main memory. The purpose of the address
field is to indicate the data address.

ADD R1, R2

Op-Code FieldAddress Fields

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• The operand field may have the following formats:

1) zero-address

2) one-address

3) two-address

4) three-address

• The total number of instructions and the types and formats of the operands
determine the length of an instruction.

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• The shorter the instruction, the faster the time that it can be fetched and
decoded.

• Shorter instructions are better than longer ones:

(i) take up less space in memory

(ii) transferred to the CPU faster

• A machine with 2^N instructions must require at least N-bit to encode all the
op-codes.

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Op-Code Encoding
A processor can execute an instruction only if it is represented as a binary sequence. A unique binary
pattern must be assigned to each op-code. This process is known as op-code encoding. An example of op-
code encoding using 3-bit block code is shown in the following table:
Op-Code Binary Pattern
LDA 000
STA 001
ADD 010
AND 011
CMA 100
INCA 101
JMP 110
HLT 111

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Op-Code Encoding Techniques
Different Op-Code encoding techniques are:

 Block-code technique

 Expanding op-code technique

 Huffman Encoding

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Block-Code Technique
- To each of the 2K instructions a unique binary bit pattern of length K is assigned.
- A K-to-2K decoder can then be used to decode all the instructions. For example,
instruction 0

instruction 1

instruction 2

3-to-8 instruction 3
3-bit Op-code decoder
instruction 4

instruction 5

instruction 6

instruction 7

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■ Expanding op-code technique
– Consider an 4+12 bit instruction with a 4-bit op-code and three 4-bit addresses.
Op-code Address Address 2 Address 3
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– It can at most encode 16 three-address instructions.

– If there are only 15 such three-address instructions, then one of the unused op-code can be
used to expand to two-address, one-address or zero address instructions.
1111 Op-code Address 1 Address 2

– Again, this expanded op-code can encode at most 16 two-address instructions. And if there
are less than 16 such instructions, we can expand the op-code further
1111 1111 Op-code Address 1

1111 1111 1111 Op-code

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Huffman Encoding
Given the probability of occurrences of each instruction, it is possible to encode all
the instructions with minimal number of bits, and with the following property:
Fewer bits are used for most frequently used instructions and more for the least frequently used ones.

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0

1/2
0
1
1/4 1

0 1

1/8 1/8 1/4 1/2

0 1 0 1 0 1 0 1

1/16 1/16 1/16 1/16 1/8 1/8 1/4 1/4

HALT JUMP SHIFT NOT AND ADD STO LOAD
0000 0001 0010 0011 010 011 10 11

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Op-Code Encoding, Huffman Codes
■ Huffman encoding algorithm:

1. Initialize the leaf nodes each with a probability of an instruction. All nodes are
unmarked.

2. Find the two unmarked nodes with the smallest values and mark them. Add a new
unmarked node with a value equal to the sum of the chosen two.

3. Repeat step (2) until all nodes have been marked except the last one, which has a value
of 1.

4. The encoding for each instruction is found by tracing the path from the unmarked node
(the root) to that instruction.

■ may mark branches arbitrarily with 0, 1 11

Op-Code Encoding, Huffman Codes (Cont.)
• Advantage:

– minimal number of bits

• Disadvantage:

– must decode instructions bit-by-bit, (can be slow).

– to decode, must have a logical representation of the encoded tree, and follow branches as we
decipher bits

– Fact is, most decoding is done in parallel

– Gives a speed advantage

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Addressing modes
■ Inherent
– an op-code indicates the address of its operand

CLI ; clear the interrupt flag

■ Immediate
– an instruction contains or immediately precedes its operand value

ADD #250, R1 % R1 := R1 + 250;

■ Absolute/Direct
– an instruction contains the memory address of its operand

ADD 250, R1 % R1 := R1 + *(250);

■ Register
– an instruction contains the register address of its operand

ADD R2, R1 % R1 := R1 + R2;

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Addressing modes (cont.)
■ Register Indirect

– the register address in an instruction specifies the address of its operand

ADD @R2, @R1 % *R1 := *R1 + *R2;

■ Auto-decrement or Auto-increment

– The contents of the register is automatically decremented or incremented

before or after the execution of the instruction

MOV (R2)+, R1 % R1 := *(R2); R2 := R2 + k;

MOV -(R2), R1 % R2 := R2 - k; R1 := *(R2);

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Addressing modes (cont.)
■ Indexed

– an offset is added to a register to give the address of the operand

MOV 2(R2), R1 % R1 := R2[2];

■ Base-register

– a displacement is added to an implicit or explicit base register to give the

address of the operand

■ Relative

– same as base-register mode except that the instruction pointer is used as the
base register

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Addressing modes (cont.)
■ Indirect addressing mode in general also applies to absolute addresses, not just
register addresses; the absolute address is a pointer to the operand.

■ The offset added to an index register may be as large as the entire address space. On
the other hand, the displacement added to a base register is generally much smaller
than the entire address space.

■ The automatic modification (i.e., auto-increment or auto-decrement) to an index

register is called auto-indexing.

■ Relative addresses have the advantage that the code is position-independent.

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Instruction Types
■ Instructions, of most modern computers, may be classified into the following five
groups:
– Data transfer

MOV, LOAD

– Arithmetic

ADD, SUB, DIV, MUL

– Logical

AND, OR, NOT, SHIFT, ROTATE

– System-control

Test-And-Set

– I/O
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Separate I/O space input/output
Instruction Types (cont.)
■ Program-control may be classified into the following four groups:
– Unconditional branch
BRB NEXT % branch to the label NEXT
– Conditional branch
SOBGTR R5, LOOP % repeat until R5=0
ADBLEQ R5, R6, LOOP % repeat until R5>R6
– Subroutine call
CALL SUB % push PC; branch to SUB
RET % pop PC
– Interrupt-handling
TRAP % generate an internal interrupt

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Instruction Types (cont.)
■ Typical branch instructions
– test the value of some flags called conditions.
– Certain instructions cause these flags to be set automatically.
■ linkage registers
– Used in implementing a subroutine.
– Typically include the instruction pointer and stack pointer..
■ The parameters passed between the caller and the called subroutine are to be established
by programming conventions.
– Very few computers support parameter-passing mechanisms in the hardware.
■ An external interrupt may be regarded as a hardware generated subroutine call
– Can happen asynchronously.
– When it occurs, the current state of the computation must be saved either by
■ the hardware automatically
■ or by a program (interrupt-service routine) control.
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