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Sap Part1

The document describes the architecture of the Simple-As-Possible (SAP)-1 computer, which is designed for educational purposes to demonstrate the basic components and functioning of a microprocessor using a limited instruction set. The SAP-1 uses an 8-bit architecture with 16 memory locations to store up to 16 instructions and can only perform addition and subtraction. It consists of a program counter, memory address register, memory, instruction register, control sequencer, accumulator, adder/subtractor, registers, and output display to fetch and execute instructions in a step-by-step manner.

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Md.Rakibul Islam
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261 views22 pages

Sap Part1

The document describes the architecture of the Simple-As-Possible (SAP)-1 computer, which is designed for educational purposes to demonstrate the basic components and functioning of a microprocessor using a limited instruction set. The SAP-1 uses an 8-bit architecture with 16 memory locations to store up to 16 instructions and can only perform addition and subtraction. It consists of a program counter, memory address register, memory, instruction register, control sequencer, accumulator, adder/subtractor, registers, and output display to fetch and execute instructions in a step-by-step manner.

Uploaded by

Md.Rakibul Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Simple-As-Possible (SAP-1)

part 1
SAP1 Malvino.pdf

Nasif M.
SAP-1
• The Simple-As-Possible (SAP)-1 computer is a very basic model of a
microprocessor explained.
• The SAP-1 design contains the basic necessities for a functional
Microprocessor.
• Its primary purpose is to develop a basic understanding of how a
microprocessor works, interacts with memory and other parts of the system
like input and output.
• The instruction set is very limited and is simple.
• SAP is Simple-As-Possible Computer. The type of computer is specially
designed for the academic purpose and nothing has to do with the
commercial use.
SAP-1
• The architecture is 8 bits and comprises of 16 X 8 memory. 16 memory
location with 8 bits in each location. All instructions (5 only) get stored in
this memory. It means SAP cannot store program having more than 16
instructions.
• SAP can only perform addition and subtraction and no logical operation.
These arithmetic operations are performed by an adder/subtractor unit.
Block diagram of
Simple-As-Possible
(SAP)-1 Architecture

CON = CP EP L’M CE’ L’I E’I L’A EA SU EU L’B L’O


SAP-1 Architecture
1. Counter Program (Program Counter)
2. Register Input & Memory Address Register (MAR)
3. 16 x 8 RAM memory
4. Register Instructions
5. Control Sequencer (Control Sequencer)
6. Accumulator A
7. Adder / Substractor
8. Register B
9. Output Register
10. Binary display
SAP-1 Architecture : 1. Program Counter

Function
It’s job is to send to the memory the address of the next instruction to be
executed and fetched.

• Control Line on Program Counter (PC):


- Ep: Transfer value from PC to Bus W
- Cp: Controls increment PC: PC PC + 1
SAP-1 Architecture : 1. Program Counter
Process
1) The PC is reset to 0000 before each computer run
2) When the computer run begins, the PC sends address 0000 to the MAR.
3) The pc is then incremented to get 0001.
MAR PC
PC PC + 1

4) After the first instruction is fetched and executed, the PC sends address
0001 to the memory.
In this way, the PC is keeping track of the next instruction to be executed.
SAP-1 Architecture : 2. Input and MAR (Memory Address Register)

Function
Its job is to hold (latched) the address of PC into Memory Address Register
(MAR)
• Control Line on Input and MAR:

- Lm: Retrieving data from bus W into MAR.


SAP-1 Architecture : 2. Input and MAR (Memory Address Register)
SAP-1 Architecture : 3. RAM

Function
The program code to be executed and data for SAP-1 computer is stored
here.

 Control Line on RAM:

- CE: Removing data 8 bit from memory to bus W.


SAP-1 Architecture : 3. RAM
• Process
1) MAR applies 4-bit address to the RAM, where a real read operation is
performed
2) Thus, the instruction or data word stored in RAM is placed on the W bus
for use by some other part of the computer.
SAP-1 Architecture : 4. Instruction register

Function
IR contains the instruction (composed of OPCODE+ADDRESS) to be
executed by SAP1 computer.

 Control Line on Instruction register:

- L1: Retrieve 8 bit data from bus W.


- E1: Controls 4 bit data from IR to bus W.
SAP-1 Architecture : 4. Instruction register
• Process
1) The contents of the IR are split into two nibbles.
2) The upper nibble is a two state output that goes directly to the block
labelled ‘Controller-sequencer’.
3) The lower nibble is send to the W-bus.
SAP-1 Architecture : 5. Controller/Sequences

Function
• It generates the control signals for each block so that actions occur in
desired sequence. CLK signal is used to synchronize the overall
operation of the SAP1 computer.

• A 12-bit word comes out of the Controller-Sequencer block. This control


word determines how the registers will react to the next positive CLK
edge.
SAP-1 Architecture : 6. Accumulator A

Function
• It is a 8-bit buffer register that stores intermediate results during a
computer run.
• It is always one of the operands of ADD, SUB and OUT instructions.

 Control Line on Accumulator A:


- La: Retrieve 8 bit data from bus W.
- Ea: Control the 8 bit data into bus W (The value appeared in the W bus)
SAP-1 Architecture : 7. Adder / Substractor

Function
• It is a 2's complement adder-subtractor.

 Control Line on Adder / Substractor:


- Su: Low signal (0) then addition operation, when signal high (1) then the
operation substraction.
- Eu: Send data to bus W
SAP-1 Architecture : 8. Register B

Function
• It is 8-bit buffer register which is primarily used to hold the other
operand (one operand is always accumulator) of mathematical
operations.

 Control Line on Register B:


- Lb: Retrieve data from bus W to register B
SAP-1 Architecture : 9. Output Register

Function
• This registers hold the output of OUT instruction.

 Control Line on Output Register:


- Lo: Retrieve data 8 bits from bus W
SAP-1 Architecture : 10. Binary display

Function
• It is a row of eight LEDs to show the contents of output register.
• Binary display unit is the output device for the SAP-1 microprocessor.
SAP-1 Architecture : Exercise

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