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Sap Part2

The document describes the instruction format and cycle of the SAP-1 computer. It has a 6-state instruction cycle with 3 states for fetching and 3 for executing instructions. The first 4 bits of an instruction are the opcode and the last 4 bits specify the operand address. Common instructions like LDA, ADD, SUB, OUT and HLT are demonstrated along with their register transfers and controller outputs over the 6 states. Timing diagrams illustrate the fetch and execute cycles.

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Md.Rakibul Islam
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71 views35 pages

Sap Part2

The document describes the instruction format and cycle of the SAP-1 computer. It has a 6-state instruction cycle with 3 states for fetching and 3 for executing instructions. The first 4 bits of an instruction are the opcode and the last 4 bits specify the operand address. Common instructions like LDA, ADD, SUB, OUT and HLT are demonstrated along with their register transfers and controller outputs over the 6 states. Timing diagrams illustrate the fetch and execute cycles.

Uploaded by

Md.Rakibul Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 35

Programming SAP-1

part 2
SAP1 Malvino.pdf

Nasif M. 1
• The instruction format of SAP-1 Computer is
(XXXX) (XXXX)
• the first four bits make the opcode while the last four bits make the
operand(address).
• SAP-1 instruction set consists of following instructions

2
Exercise 1

• Q: Translate the program into SAP1 machine language.


• Program:

3
Answer:

• Machine language:

4
Exercise 2

• Q: Write down the program (assembly language and machine language) to


get the result in SAP1 for the following arithmetical expression.
16 + 20 + 24 -32 (decimal)

5
Answer:

• Assembly language:

6
Answer:

• Machine language:

The program is
stored in the low-
memory. And data is
stored in the high-
memory.

7
Machine cycle and Instruction cycle

SAP1 has six T-states (three fetch and three execute cycles) reserved for each
instruction. Not all instructions require all the six T-states for execution. The
unused T- state is marked as No Operation (NOP) cycle. Each T-state is called a
machine cycle for SAP1. A ring counter is used to generate a T-state at every
falling edge of clock pulse. The ring counter output is reset after the 6th T-
state.

FETCH CYCLE – T1, T2, T3 machine cycle

EXECUTE CYCLE - T4, T5, T6 machine cycle

8
Ring counter

Figure: a. Ring counter symbol


b. Clock and timing signals

9
Ring counter

10
Machine cycle and Instruction cycle

SAP1 has six T-states (three fetch and three execute cycles) reserved for each
instruction. Not all instructions require all the six T-states for execution. The
unused T- state is marked as No Operation (NOP) cycle. Each T-state is called a
machine cycle for SAP1. A ring counter is used to generate a T-state at every
falling edge of clock pulse. The ring counter output is reset after the 6th T-
state.

11
FETCH CYCLE
FETCH CYCLE – T1, T2, T3 machine cycle

T1 (address state),
T2 (Increment state),
T3 machine cycle (Memory state)

12
EXECUTE CYCLE
EXECUTE CYCLE - T4, T5, T6 machine cycle

The next three states (T4, T5, T6) are the execution cycle of SAP1. The
register transfers during the execution cycle depend on the particular
instruction being executed. For example, LDA 9H requiers different register
transfer than ADD BH.

13
Instruction routine
• LDA routine
• ADD routine
• SUB routine T1, T2, T3 machine cycle
• OUT routine is same for all instruction
• HLT routine

14
Block diagram of
Simple-As-Possible
(SAP)-1 Architecture

CON = CP EP L’M CE’ L’I E’I L’A EA SU EU L’B L’O


FETCH CYCLE

16
Fetch cycle : T1, T2, T3

17
T1: Address state

18
T2: Increment state

19
T3: memory state

20
EXECUTE CYCLE

21
LDA routine (a) T4 state (b) T5 state (c) T6 state

22
LDA routine (a) T4 state
•Let’s
  assume that the instruction
register has been loaded with LDA
9H:
IR = 0000 1001
T4 state: The instruction field 0000
goes to the controller-sequencer,
where it is decoded. The address
field 1001 is loaded into the MAR.
At this state, and are active.
The controller sequence word is:

000 1 1010 00 11
23
LDA routine (b) T5 state
•T5  state: During T5 state, and go
low (active). The addressed data
word in the RAM will loaded into
the accumulator.
The controller sequence word is:

001 0 1100 00 11

24
LDA routine (c) T6 state
T6 state: T6 state is non-
operational for LDA routine, all
registers all inactive. This means
that the controller-sequencer is
sending out a word whose bits all
inactive. The T6 state of LDA
routine is inactive.
The controller sequence word is:

001 1 1110 00 11

25
Timing diagram showing LDA routine
(Fetch cycle and Execute cycle)

26
ADD routine (a) T4 state (b) T5 state (c) T6 state

27
ADD routine (a) T4 state
•Let’s
  assume that at the end of the
fetch cycle the instruction register
contains ADD BH:
IR = 0001 1011
T4 state: The instruction field 0001
goes to the controller-sequencer,
where it is decoded. The address
field 1011 is loaded into the MAR.
At this state, and are active.
The controller sequence word is:

000 1 1010 00 11
28
ADD routine (b) T5 state
•T5  state: During T5 state, and go
low (active). The addressed data
word in the RAM will loaded into
the Register B.
The controller sequence word is:

001 0 1110 00 01

29
ADD routine (c) T6 state
•T6  state: During T6 state, and go
low (active). The adder/subtractor
Su (0)
is activated.
The controller sequence word is:

001 1 1100 01 11

30
Timing diagram showing ADD routine
(Fetch cycle and Execute cycle) CLK

31
SUB routine (a) T4 state (b) T5 state (c) T6 state

Su (1)

32
OUT routine (a) T4 state

33
OUT routine (a) T4 state

34
HLT routine

35

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