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Don'T-Care Conditions

This document discusses don't-care conditions in Boolean logic. Don't-care conditions occur when the output of a Boolean function is unspecified for certain input combinations. These don't-care conditions, represented by X, can be grouped with 1s or 0s during simplification to produce the simplest expression. Simplifying a function using don't-care conditions allows for further reduction of the Boolean expression.

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42 views8 pages

Don'T-Care Conditions

This document discusses don't-care conditions in Boolean logic. Don't-care conditions occur when the output of a Boolean function is unspecified for certain input combinations. These don't-care conditions, represented by X, can be grouped with 1s or 0s during simplification to produce the simplest expression. Simplifying a function using don't-care conditions allows for further reduction of the Boolean expression.

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muktikanta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DON’T-CARE CONDITIONS

DON’T-CARE CONDITIONS
• The logical sum of the minterms associated with a Boolean
function specifies the conditions under which the function is
equal to 1. The function is equal to 0 for the rest of the minterms.

• This pair of conditions assumes that all the combinations of the


values for the variables of the function are valid.

• In practice, in some applications the function is not specified for


certain combinations of the variables. As an example, the four-bit
binary code for the decimal digits has six combinations that are
not used and consequently are considered to be unspecified
DON’T-CARE CONDITIONS
• Functions that have unspecified outputs for some
input combinations are called incompletely specified
functions . In most applications, we simply don’t care
what value is assumed by the function for the
unspecified minterms.

• For this reason, it is customary to call the unspecified


minterms of a function don’t-care conditions . These
don’t-care conditions can be used on a map to provide
further simplification of the Boolean expression.
DON’T-CARE CONDITIONS
• A don’t-care minterm is a combination of variables whose logical
value is not specified.

• Such a minterm cannot be marked with a 1 in the map, because it


would require that the function always be a 1 for such a
combination. Likewise, putting a 0 on the square requires the
function to be 0.

• To distinguish the don’t-care condition from 1’s and 0’s, an X is


used. Thus, an X inside a square in the map indicates that we don’t
care whether the value of 0 or 1 is assigned to F for the particular
minterm.
DON’T-CARE CONDITIONS
• In choosing adjacent squares to simplify the
function in a map, the don’t-care minterms
may be assumed to be either 0 or 1.

• When simplifying the function, we can choose


to include each don’t-care minterm with
either the 1’s or the 0’s, depending on which
combination gives the simplest expression.
HDL Description of The Simplified
Function
F = YZ+W’X’
// Verilog model: Circuit with Boolean expressions
module Circuit (F, W, X, Y, Z);
Output F;
Input W, X, Y, Z;
assign F = (Y && Z ) || ((! W) && (! X) );
endmodule
HDL Description of The Simplified
Function
F = (A’+B’)(C’+D’)(B’+D)
// Verilog model: Circuit with Boolean expressions
module Circuit (F, A,B,C,D);
Output F;
Input A, B, C, D;
assign F = ((! A) || (! B) ) && ((! C) || (! D) ) && ((! B) || D );
endmodule

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