Lecture

Lecture 21alt
21alt
BIST
BIST --
-- Built-In
Built-In Self-Test
Self-Test
(Alternative
(Alternative to
to Lectures
Lectures 25,
25, 26
26 and
and 27)
27)
 Definition of BIST
 Pattern generator
 LFSR

 Response analyzer
 MISR

 Aliasing probability

 BIST architectures
 Test per scan

 Test per clock

 Circular self-test

 Memory BIST

 Summary
Copyright 2005, Agraw VLSI Test: Lecture 21alt 1
al & Bushnell
 Define
Define Built-In
Built-In Self-Test
Self-Test
 Implement the function of automatic test equipment
(ATE) on circuit under test (CUT).
 Hardware added to CUT:
 Pattern generation (PG)
 Response analysis (RA)
 Test controller CK PG

Test control logic

Stored
Pin
Test
Patterns
Electronics CUT
Test control HW/SW CUT BIST RA
Stored Comparator Enable
responses hardware
ATE Go/No-go
signature
Copyright 2005, Agraw VLSI Test: Lecture 21alt 2
al & Bushnell
 Pattern
Pattern Generator
Generator (PG)
(PG)
 RAM or ROM with stored deterministic patterns
 Counter
 Pseudorandom pattern generator
 Feedback shift register

 Cellular automata

Copyright 2005, Agraw VLSI Test: Lecture 21alt 3

al & Bushnell
 Pseudorandom
Pseudorandom Integers
Integers
Xk = Xk-1 + 3 (modulo 8) Xk = Xk-1 + 2 (modulo 8)

0 0
7 1 7 1

6 2 Start 6 2 Start
+3
+2
5 3 5 3
4 4

Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . . Sequence: 2, 4, 6, 0, 2 . . .
Maximum length sequence: 3 and 8 are relative primes.
Copyright 2005, Agraw VLSI Test: Lecture 21alt 4
al & Bushnell
 Pseudo-Random
Pseudo-Random Pattern
Pattern
Generation
Generation
 Standard Linear Feedback
Shift Register (LFSR)
 Produces patterns

algorithmically –
repeatable
 Has most of desirable

random # properties
 May not cover all 2n input
combinations either hi = 0, i.e., XOR is deleted
 Long sequences needed or hi = X i
for good fault coverage Initial state (seed): X0, X1, . . . , Xn-1
must not be 0, 0, . . . , 0

Copyright 2005, Agraw VLSI Test: Lecture 21alt 5

al & Bushnell
 Matrix
Matrix Equation
Equation for
for
Standard
Standard LFSR
LFSR

X0 (t + 1) 0 1 0 … 0 0 X0 (t)
0 0 1 … 0 0
X1 (t + 1) . . . . . X1 (t)
. . . . .
. = . . . . . .
. 0 … 1 0 .
. 0 0 .
Xn-3 (t + 1) 0 0 0 … 0 1 Xn-3 (t)
1 h1 h2 … hn-2 hn-1
Xn-2 (t + 1) Xn-2 (t)
Xn-1 (t + 1) Xn-1 (t)
X (t + 1) = Ts X (t) (Ts is companion matrix)

Copyright 2005, Agraw VLSI Test: Lecture 21alt 6

al & Bushnell
 LFSR
LFSR Implements
Implements a
a
Galois
Galois Field
Field
 Galois field (mathematical system):
 Multiplication by X same as right shift of LFSR

 Addition operator is XOR (

)
 Ts companion matrix:
 1st column 0, except nth element which is always 1

(X0 always feeds back)

 Rest of row n – feedback coefficients h
i
 Remaining identity matrix means a right shift

 Near-exhaustive (maximal length) LFSR

 Cycles through 2n – 1 states (excluding all-0)

Copyright 2005, Agraw VLSI Test: Lecture 21alt 7

al & Bushnell
 LFSR
LFSR Properties
Properties
 Must not initialize to all 0’s – hangs
 If X is initial state, LFSR progresses through states
X, Ts X, Ts2 X, Ts3 X, …
 Matrix period:
Smallest k such that Tsk = I
 k = LFSR cycle length
 Maximum length k = 2n-1, when feedback (characteristic)
polynomial is primitive
 Example: 1 + X+ X3
 Characteristic polynomial:
1 + h1 x + h2 X2 + … + hn-1 Xn-1 + Xn

Copyright 2005, Agraw VLSI Test: Lecture 21alt 8

al & Bushnell
 LFSR:
LFSR: 1
1++X
X++X
X 33

RESET
100 001

000
010
110
D Q D Q D Q
X2 X1 X0 101
111
011
CK

RESET
X2 X1 X0

Test of primitiveness: Characteristic polynomial of degree n

must divide 1 + Xq for q = n, but not for q < n

Copyright 2005, Agraw VLSI Test: Lecture 21alt 9

al & Bushnell
LFSR
LFSR as
as Response
Response Analyzer
Analyzer
 Use cyclic redundancy check code (CRCC) generator
(LFSR) for response compacter
 Treat data bits from circuit POs to be compacted as a
decreasing order coefficient polynomial
 CRCC divides the PO polynomial by its characteristic
polynomial
 Leaves remainder of division in LFSR

 Must initialize LFSR to seed value (usually 0) before

testing
 After testing – compare signature in LFSR to
precomputed signature of fault-free circuit

Copyright 2005, Agraw VLSI Test: Lecture 21alt 10

al & Bushnell
 Example
Example Modular
Modular LFSR
LFSR
Response
Response Analyzer
Analyzer

 LFSR seed is “00000”

Copyright 2005, Agraw VLSI Test: Lecture 21alt 11

al & Bushnell
Signature
Signature by
by Logic
Logic Simulation
Simulation
Input bits X0 X1 X2 X3 X4
Initial State 0 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 0 0 1 0
1 1 0 0 0 1
0 1 0 0 1 0
1 1 1 0 0 1
0 1 0 1 1 0 Signature

Copyright 2005, Agraw VLSI Test: Lecture 21alt 12

al & Bushnell
 Signature
Signature by
by Polynomial
Polynomial
Division
Division
Input bit stream: 0 1 0 1 0 0 0 1

0 ∙ X0 + 1 ∙ X1 + 0 ∙ X2 + 1 ∙ X3 + 0 ∙ X4 + 0 ∙ X5 + 0 ∙ X6 + 1 ∙ X7

X2 + 1
X5 + X3 + X + 1 +X
+ X3
Char. polynomial X7
+ X5 + X3 + X2
X7 +X
5 2
X +X
+X +1
remainder X5 + X3 +1
+1
Signature: X0 X1 X2 X3 X4 = X130 1 X20
Copyright 2005, Agraw VLSI Test: Lecture 21alt 13
al & Bushnell
 Multiple-Input
Multiple-Input Signature
Signature
Register
Register (MISR)
(MISR)
 Problem with ordinary LFSR response compacter:
 Too much hardware if one of these is put on each

primary output (PO)

 Solution: MISR – compacts all outputs into one LFSR
 Works because LFSR is linear – obeys

superposition principle
 Superimpose all responses in one LFSR – final

remainder is XOR sum of remainders of polynomial

divisions of each PO by the characteristic
polynomial

Copyright 2005, Agraw VLSI Test: Lecture 21alt 14

al & Bushnell
 Modular
Modular MISR
MISR Example
Example

X0 (t + 1) 0 0 1 X0 (t) d0 (t)
= 1 0 1 +
X1 (t + 1) 0 1 0 X1 (t) d1 (t)
X2 (t + 1) X2 (t) d2 (t)
Copyright 2005, Agraw VLSI Test: Lecture 21alt 15
al & Bushnell
 Aliasing
Aliasing Probability
Probability
 Aliasing means that faulty signature matches fault-
free signature
 Aliasing probability ~ 2-n
 where n = length of signature register

 Example 1: n = 4, Aliasing probability = 6.25%

 Example 2: n = 8, Aliasing probability = 0.39%

 Example 3: n = 16, Aliasing probability = 0.0015%

Fault-free 2n-1 faulty

signature signatures

Copyright 2005, Agraw VLSI Test: Lecture 21alt 16

al & Bushnell
 BIST
BIST Architectures
Architectures

 Test per scan

 Test per clock
 Circular self-test
 Memory BIST

Copyright 2005, Agraw VLSI Test: Lecture 21alt 17

al & Bushnell
 Test
Test Per
Per Scan
Scan BIST
BIST
PG Scan register PI and PO
disabled
Comb. logic during test

Scan register
BIST
BIST Go/No-go Comb. logic
Control
enable signature
logic
Scan register

Comb. logic

RA Scan register

Copyright 2005, Agraw VLSI Test: Lecture 21alt 18

al & Bushnell
 Test
Test per
per Clock
Clock BIST
BIST
 New fault set tested every clock period
 Shortest possible pattern length
 10 million BIST vectors, 200 MHz test / clock
 Test Time = 10,000,000 / 200 x 106 = 0.05 s
 Shorter fault simulation time than test / scan

Copyright 2005, Agraw VLSI Test: Lecture 21alt 19

al & Bushnell
 Circular
Circular Self
Self Test
Test

Copyright 2005, Agraw VLSI Test: Lecture 21alt 20

al & Bushnell
 Built-in
Built-in Logic
Logic Block
Block
Observer
Observer (BILBO)
(BILBO)
 Combined functionality of D flip-flop, pattern generator,
response analyzer, and scan chain
 Reset all FFs to 0 by scanning in zeros

Copyright 2005, Agraw VLSI Test: Lecture 21alt 21

al & Bushnell
 Test
Test per
per Clock
Clock with
with BILBO
BILBO
 SI – Scan In
 SO – Scan Out
 Characteristic polynomial: 1 + x + … + xn
 CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR
 CUT B: BILBO1 is LFSR, BILBO2 is MISR

Copyright 2005, Agraw VLSI Test: Lecture 21alt 22

al & Bushnell
 BILBO
BILBO Serial
Serial Scan
Scan Mode
Mode
 B1 B2 = “00”
 Dark lines show enabled data paths

Copyright 2005, Agraw VLSI Test: Lecture 21alt 23

al & Bushnell
 BILBO
BILBO LFSR
LFSR Pattern
Pattern
Generator
Generator Mode
Mode
 B1 B2 = “01”

Copyright 2005, Agraw VLSI Test: Lecture 21alt 24

al & Bushnell
 BILBO
BILBO in
in DFF
DFF (Normal)
(Normal)
Mode
Mode
 B1 B2 = “10”

Copyright 2005, Agraw VLSI Test: Lecture 21alt 25

al & Bushnell
 BILBO
BILBO in
in MISR
MISR Mode
Mode
 B1 B2 = “11”

Copyright 2005, Agraw VLSI Test: Lecture 21alt 26

al & Bushnell
 Memory
Memory BIST
BIST

Copyright 2005, Agraw VLSI Test: Lecture 21alt 27

al & Bushnell
 Summary
Summary
 LFSR pattern generator and MISR response analyzer –
preferred BIST methods
 BIST has overheads: test controller, extra circuit
delay, primary input MUX, pattern generator, response
compacter, DFT to initialize circuit and test the test
hardware
 BIST benefits:
 At-speed testing for delay and stuck-at faults

 Drastic ATE cost reduction

 Field test capability

 Faster diagnosis during system test

 Less effort to design testing process

 Shorter test application times

Copyright 2005, Agraw VLSI Test: Lecture 21alt 28

al & Bushnell