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Digital Signal Processors and Architectures (DSPA) Unit-2

This document discusses the basic architectural features of programmable DSP devices. It describes the basic building blocks like multipliers, shifters, MAC units and ALUs. It also discusses bus architectures, on-chip memory organizations, addressing modes, programmability and techniques to improve speed like pipelining and parallelism. The document focuses on key components that help accelerate common DSP functions and algorithms.

Uploaded by

Chaitanya Duggineni
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
552 views92 pages

Digital Signal Processors and Architectures (DSPA) Unit-2

This document discusses the basic architectural features of programmable DSP devices. It describes the basic building blocks like multipliers, shifters, MAC units and ALUs. It also discusses bus architectures, on-chip memory organizations, addressing modes, programmability and techniques to improve speed like pipelining and parallelism. The document focuses on key components that help accelerate common DSP functions and algorithms.

Uploaded by

Chaitanya Duggineni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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UNIT-2

Architectures for Programmable


DSP Devices
Basic Architectural Features
Basic Architectural Features
Basic Architectural Features
Basic Building blocks
• Multiplier
• Shifter
• Multiply and accumulate (MAC) unit
• Arithmetic Logic Unit (ALU)
Multiplier
Parallel Multiplier
Parallel Multiplier
Multiplier

4 x4 Binary Multiplication
Parallel Multiplier
• Unsigned numbers:
m 1
A =  Ai 2i
i= 0
n 1
B =  Bj 2 j
j= 0

 m 1
n 1
i+ j 
P = AB =   Ai B j 2 
j= 0  i= 0 
Multiplier for Signed Numbers

m2
A   Am1 2 m 1
  Ai 2 i

i 0
n2
B   Bn1 2 n 1
  Bj 2 j

j 0
Parallel Multiplier

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Shifter
Shifter
Barrel Shifter
Shifter
• Barrel Shifter:
Barrel Shifter
Barrel Shifter
Barrel Shifter
Multiplier and Accumulate (MAC)
Unit
Multiplier and Accumulate (MAC)
Unit
MAC Unit
MAC Unit
MAC Unit
MAC Unit Overflow and Underflow
Saturation logic: Overflow
Arithmetic Logic Unit
Arithmetic Logic Unit
Bus Architecture and Memory

• Von Neumann architectures


• Harvard architectures
Bus Architecture and Memory
Bus Architecture and Memory
Bus Architecture and Memory
Bus Architecture and Memory

On-Chip Memory
Bus Architecture and Memory

On-Chip Memory
Bus Architecture and Memory

Practical Organization of On-Chip Memory


Bus Architecture and Memory

Practical Organization of On-Chip Memory


Data Addressing capabilities
Data Addressing capabilities
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Data Addressing capabilities
Data Addressing capabilities
Data Addressing capabilities
Data Addressing capabilities
Data Addressing capabilities
Special Addressing modes

• Circular addressing: three registers


– Pointer Register (PNTR)
– Start address register (SAR)
– End address register (EAR)
Special Addressing modes
Circular addressing:
Four cases:
1)SAR < EAR, updated PNTR > EAR
2)SAR < EAR, updated PNTR < SAR
Buffer size = EAR – SAR +1
1)SAR > EAR, updated PNTR > SAR
2)SAR > EAR, updated PNTR < EAR
Buffer size = SAR – EAR +1
Different cases of Circular addressing:

SAR< EAR updated PNTR>EAR SAR<EAR updated PNTR<SAR


New PNTR Updated PNTR – Buffer size New PNTR Updated PNTR + Buffer size
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Different cases of Circular addressing:

SAR> EAR updated PNTR>SAR SAR>EAR updated PNTR<EAR


New PNTR Updated PNTR – Buffer size New PNTR Updated PNTR + Buffer
size
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Special Addressing modes
• Circular addressing
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Data Addressing capabilities
Bit Reversed Addressing mode

Current index= Previous index+ B (1/2(FFT Size))


 Compute the indices for an 8-point FFT using Bit
reversed Addressing Mode
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Address Generation Unit
a. Getting value from immediate operand, register or a
memory location.
b. Incrementing/ decrementing the current address.
c. Adding/subtracting the offset from the current address.
d. Adding/subtracting the offset from the current address and
generating new address according to circular addressing
mode.
e. Generating new address using bit reversed addressing
mode.
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Programmability and Program Control
Program Control:
• Microcoded control used in microprocessors is replaced with
hardwired design in DSP processors.
• Microcoded control:
• Easy to design and implement
• Uses less hardware
• Not very fast
• Hardwired control:
• Hardware complexity is high
• Design is not easy to change
•31/12/20Much faster, reduces the overhead for instruction execution time.
Programmability and Program Control
Program Sequencer

The next address can be from:

a. Program Counter

b. Instruction reg. in case of branching, looping and


subroutine calls

c. Interrupt Vector table

d. Stack which holds the return address


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Speed Issues

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Speed Issues
1. Hardware Architecture:
• Parallel multipliers
• Hardwired control
• Harvard architecture
• On-chip memories

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Hardware Architecture

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Parallelism

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Speed Issues
2. Parallelism:
• Provision of functional units
• Multiple memories and multiple buses
• Eg: MAC operation

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Pipelining

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Pipelining

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Speed Issues
3. Pipelining:
2 Issues:
• Dividing each instruction into steps
• Pipeline latency
• In case of branch or loop, pipeline needs to
be cleared.

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System Level Parallelism and Pipelining

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System Level Parallelism and Pipelining

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System Level Parallelism and Pipelining

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System Level Parallelism and Pipelining

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Implementation Using a Single MAC Unit

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Pipelined Implementation: 8 Multipliers and 8
Accumulators

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Parallel Implementation: Two MAC Units

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Features of External Interfacing
• Interface for interrupts
• Direct memory access
• Serial I/O
• Parallel I/O
• ADC
• DAC
• Timer

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