University of Gujrat

Department of Computer Science

Course Code : CS-252

Computer Organization and Assembly Language

1 Lecture # 2
Basic Computer Organization

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2 Basic Computer Organization

 A computer system comprises of

Memory
Processor, Memory and I/O devices.
 I/O is used for interfacing with the
external world, while memory is the
processor’s internal world. Processor
 Processor is the core component and is
responsible for performing operations.

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I/O
 Interconnection between
3
Components

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4 Interconnection between Components
 The processor performs an operation on data, which resides
in memory.
 A mechanism is required for the processor to read data
from the memory.

Processor
Memory Data
Operation

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5
Address, Data and Control Buses
 There must be a mechanism to inform memory that we want
to do the read operation
 Control Bus
 There must be a mechanism to inform memory that we want
to read precisely which element
 Address Bus
 There must be a mechanism to transfer that data element
from memory to processor
 Data Bus
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6 Bus
 The process may be able to communicate with all the devices. The devices are
connected together by communication channel called a BUS.
 A bus is composed of a set of communication lines or wires.
 It is used to move large amount of bits in form of electrical pulses from a
specified source to a specified destination.

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7 Control, Address and Data Buses
 The group of lines that carry control information from the control unit to the other units is
the Control Bus
 The group of lines that carries the address information is the Address Bus
 The group of wires or lines that moves data between the different components is the Data
Bus
For e.g.
If the processor wants to read data from the address ‘135Fh’ of memory

135Fh
Address Bus
2
Processor Data Bus
Memory
Read
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8 Control, Address and Data Buses

Address Bus

Data Bus
Processor Memory
Control Bus

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9 What do buses look like?

 Parallel lines on circuit

boards
 Ribbon cables
Fig. Parallel lines Fig. Ribbon Cables
 Strip connectors on
mother boards
e.g. PCI
 Set of wires
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Fig. connectors Fig. Set of wires

10
Basic Memory Organization
Information processed by a computer is stored in its memory.

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11 Memory Byte
Address Contents
 Memory circuit element can store one bit of data.
 Memory circuits are organized into groups that can
store 8 bits of data called Memory Byte.
 Each memory byte is identified a number that is
called its Address. 4 01011011
 Contents of Memory Byte are always 8 bits but the
3 11001001
number of bits in an address depends upon the
processor. 2 01011011
1 01000010
For e.g.
0 00011000
Intel 8086 microprocessor assigns a 20-bit address

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12 Memory Word

 Memory Word is any pair of

successive memory bytes treated as a
single unit 3 01000010
2 00011000
 The lower address is used as the
Address
address of the memory word. Memory Word

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13 Memory Operations

 The processor can perform following two operation on memory:

1. Read ( fetch the contents of a location )

2. Write ( store data at a location )

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14 RAM and ROM
There are two kinds of memory circuits:
1. Random Access Memory (RAM)
2. Read Only Memory (ROM)

RAM ROM
 RAM locations can be Read and Written  ROM location can only be Read
 Volatile  Non-Volatile
 Programs instructions and data are  Used by manufactures to store system
normally loaded into RAM programs. ROM based programs are
known as Firmware

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15
CPU Organization

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16
CPU
 Brain of the computer
 Controls the computer by executing programs stored in memory
 Each instruction executed by it, is a bit string
 Instructions performed by a CPU is called the Instruction Set.
Instruction set for each CPU is unique.
There are two functional units:
1. Execution Unit (EU)
2. Bus Interface Unit (BIU)

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17

Intel 8086 Micro Processor Organization

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18 Execution Unit (EU)

 Executes instructions
 Contains circuits called Arithmetic and Logic Unit
 Contains 8 registers for storing data
AX, BX, CX, DX, SI, DI, BP and SP
 Contains temporary registers for holding operands for the ALU
 FLAG registers whose individual bits reflect the result of a
computation

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19
Bus Interface Unit (BIU)

 Facilitates communication between the EU and the memory or I/O

circuits
 Contains registers CS, DS, ES, SS and IP for holding addresses of
memory locations
 EU and BIU connected by an Internal Bus
 While EU is executing an instruction. BIU fetches next instruction
and places it in the instruction queue, this is called instruction
prefetch

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20
Instruction Execution Cycle
(Fetch-Execute Cycle)

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21 Fetch-Execute Cycle

Fetch

Execute

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 THE END
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