Logic Synthesis

Timing Analysis

Courtesy RK Brayton (UCB) 1

and A Kuehlmann (Cadence)
Timing Analysis - Delay Models
• Simple model 1:
Ak
Dk

A3
A1
A2
Ak = arrival time = max(A1,A2,A3) + Dk
Dk is the delay at node k, parameterized according to function fk and
fanout node k

• Simple model 2: Ak Ak = max{A1+Dk1,

Ak 0 A2+Dk2,A3+Dk3}
 Dk1 Dk2 Dk3
A3
A1 A3
A2 A1 A2
2
• Can also have different times for rise time and fall time
Static delay analysis
// level of PI nodes initialized to 0,
// the others are set to -1.
// Invoke LEVEL from PO
Algorithm LEVEL(k) { // levelize nodes
if( k.level != -1)
return(k.level)
else
k.level = 1+max{LEVEL(ki)|ki  fanin(k)}
return(k.level)
}

// Compute arrival times:

// Given arrival times on PI’s
Algorithm ARRIVAL() {
for L = 0 to MAXLEVEL
for {k|k.level = L}
Ak = MAX{Aki} + Dk
}

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Required Times
Sk Sj
k
Required times: j

given required times on primary outputs Ski

ki ki

• Traverse in reverse topological order (i.e. from primary outputs

to primary inputs)
• if (ki , k ) is an edge between ki and k, Rki ,k = Rk - Dk
(this is the edge required time)
• Hence, the required time of output of node k is
Rk = min ( Rk,kj | kj  fanout(k) )

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 Propagating Slacks
Slacks: slack at the output node k is Sk = Rk-Ak Sk Sj
Since Rki,k=Rk-Dk k
Ski,k =Rki,k - Aki j
Ski,k + Aki = Rk-Dk = Sk + Ak - Dk
Since Ak = max {Akj } + Dk Ski
ki ki
Ski,k = Sk + max {Akj } - Aki kj , ki  fanin (k )
Ski = min{Ski,j} j  fanout (ki )

Notes:
• Each edge is the graph has a slack and a required time
• Negative slack is bad.

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Sequential networks

C2
C1
l1 l4

C3 C4
l2 l3
l5

• Arrival times known at l1 and l2

• Required times known at l3, l4, and l5
• Delay analysis gives arrival and required times (hence slacks)
for C1, C2, C3, C4

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Static critical paths
Min-Max problem: minimize max{-Si , 0}

A static critical path of a Boolean network is a path P = {i1,i2,…,ip }

where Sik, ik+1 < 0

Note: if a node k is on a static critical path, then at least one of the

fanin edges of k is critical. Hence, all critical paths reach from an
input to an output.
Note: There may be several critical paths

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 Example: Static critical paths
A1=6 R1=5
A2=5 R2=5
R1=5 R2=5
S1=-1 R3=3
6 -1 5 0 S2=0 R7=1
S3,1=-1 R9=-1
1 2 1 2
S4,1 = -1
-1 1 S4,2 = 0
4 -1 4 0 3 S5,2 = 1
3 2 2 4 1 5 S6,3 = 0
S7,3 = -1
-1 -1 S7,4 = -1
0 1
1 2 S7,5 = 1
1 6 2 7 S8,6 = 0
S9,7 = -1
0 -1
8 9 critical path edges
A9=0
A8=0 Ski,k = Sk + max{Akj } - Aki , kj,ki  fanin(k)
Sk = min{Sk,kj }, kj  fanout(k)
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Timing analysis problems
We want to determine the true critical paths of a circuit in order to:
– determine the minimum cycle time that the circuit will function
– identify critical paths from performance optimization - don’t want to
try to optimize the wrong (non-critical) paths
Implications:
– Don’t want false paths (produced by static delay analysis)
– Delay model is worst case model. Need to ensure correctness for
case where ith gate delay  DiM

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 Functional Timing Analysis

What is Timing Analysis?

Estimate when the output of a given circuit gets stable

Combinational
block
0
0 T
clock
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Why Timing Analysis?
Timing verification
– Verifies whether a design meets a given timing constraint
• Example: cycle-time constraint
Timing optimization
– Needs to identify critical portion of a design for further
optimization
• Critical path identification
In both applications, the more accurate, the better

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Timing Analysis - Basics
Naïve approach - Simulate all input vectors with SPICE
– Accurate, but too expensive
Gate-level timing analysis
Focus of this lecture
– Less accurate than SPICE due to the level of abstraction,
but much more efficient
– Scenario:
• Gate/wire delays are pre-characterized (accuracy loss)
• Perform timing analysis of a gate-level circuit assuming
the gate/wire delays

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 Gate-level Timing Analysis
False A naive approach is topological analysis
path – Easy longest-path problem
aware z – Linear in the size of a network
arr(z)? Not all paths can propagate signal events
1 – False paths
– If all longest paths are false,
topological analysis gives delay
overestimate
1 Functional timing analysis = false-path-
aware timing analysis
– Compute false-path-aware arrival time

x1 x2
arr(x1)=0 arr(x2)=0
 Example: 2-bit Carry-skip Adder

c_in s0

Length 1
Length 5
a0
s1
b0
1
0
a1 c_out
b1

mux
ripple carry adder
False Path Analysis - Basics
Is a path responsible for delay?
– If the answer is no, can ignore the path for delay computation
Check the falsity of long paths until we find the longest true path
– How can we determine whether a path is false?

Delay underestimation is unacceptable

– Can lead to overlooking a timing violation
Delay overestimation is not desirable, but acceptable
– Topological analysis can give overestimate, but never give
underestimate

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 Controlling/Non-Controlling Values
Controlled value of AND

0 0 1

Controlling value of AND Non-Controlling value of AND

Controlled value of OR
1 1
1 0

Controlling value of OR
Non-Controlling value of OR

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Static Sensitization
A path is statically-sensitizable if there exists an input vector such
that all the side inputs to the path are set to non-controlling
values
– This is independent of gate delays
Controlling value!
1
0

t=0
t=0
These paths are not
1 statically-sensitizable
t=0 0
The longest true path
is of length 2? 17
Static Sensitization
• The (dashed) path is responsible for delay!
• Delay underestimation by static sensitization (delay = 2 when
true delay = 3)
– incorrect condition

1
0
2 3
1
0
2
0

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What is Wrong with Static Sensitization?

The idea of forcing non-controlling values to side inputs

is okay, but timing was ignored
– The same signal can have a controlling value at one time
and a non-controlling value at another time.

How about timing simulation as a correct method?

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Timing Simulation

0 2
2
2 3
1
1
1
1
4

0 44
Implies that delay = 0 for these inputs
BUT!
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Timing Simulation

0 2
2
2 3
1
1 3 4
1
1
4->2

0 22

Implies that delay = 4 with the same set of

inputs. 21
What is Wrong with Timing Simulation?

If gate delays are reduced, delay estimates can

increase

Not acceptable since

– Gate delays are just upper-bounds, actual delay is in [0,d]
• Delay uncertainty due to manufacturing
– We are implicitly analyzing a family of circuits where gate
delays are within the upper-bounds

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Monotone Speedup Property
Definition: For any circuit C, if
– C’ is obtained from C by reducing some gate delays, and
– delay_estimate(C’)  delay_estimate(C),
then delay_estimate has Monotone Speedup property

Timing simulation does not have this property

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Timing Simulation Revisited

0 2
2
3
1
1 4
1
1
4

0 44
means that the rising signal
occurs anywhere between
4 t = -infinity and t = 4.
X-valued simulation 24
Timing Simulation Revisited
Timed 3-valued (0,1,X) simulation
– called X-valued simulation
Monotone speedup property is satisfied.

Underlying model of
• floating mode condition [Chen, Du]
– Applies to “simple gate” networks only
• viability [McGeer, Brayton]
– Applies to general Boolean networks
False Path Analysis Algorithms
Checking the falsity of every path explicitly is too expensive - exponential # of
paths
State-of-the-art approach:
1. Start: set L = Ltop-  = topological longest path delay - 
Lold = 0
2. Binary search:
If (Delay(L)) (*)
L = |L-Lold|/2, Lold = L, L = L +  L
Else,  L = |L-Lold|/2, Lold = L, L = L -  L
If (L > Ltop or  L < threshold), L = Lold , done

* Delay(L) = 1 if there an input vector under which an output gets stable only at time t
( )

where L  t ?
Can be reduced to
– a SAT problem [McGeer, Saldanha, Brayton, ASV] or
– a timed-ATPG [Devadas, Keutzer, Malik]
SAT-based False Path Analysis

Decision problem:
Is there an input vector under which the output gets stable only after t = T ?
Idea:
1. characterize the set of all input vectors S(T) that make the output
stable no later than t = T
2. check if S(T) contains S = all possible input vectors
This check is solved as a SAT problem:
Is S \ S(T) empty? - set difference + emptiness check
• Let F and F(T) be the characteristic functions of S and S(T)
• Is F !F(T) satisfiable?

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Example

d
g
a
b e f
c

Assume all the PIs arrive at t = 0, all gate delays = 1

Is the output stable time t > 2?

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Example
g(1,t=2) : the set of input vectors under which
g gets stable to value = 1 no later than t =2
d
g
a
b e f
Onset:
stabilized by t=2?
c
g(1,t=2) = d(1,t=1)  f(1,t=1)
= (a(0,t=0)  b(0,t=0))  (c(1,t=0) e(1,t=0))
= !a!b(c ) = !a!bc = S1(t=2)
g(1,t=) = onset = !a!bc = g(1,t=2) = S1 29
Example
g(0,t=2) : the set of input vectors under which
g gets stable to value = 0 no later than t=2
d
g
a
b e f

c
g(0,t=2) = d(0,t=1)  f(0,t=1)
= (a(1,t=0)  b(1,t=0))  (c(0,t=0)  e(0,t=0))
= (a+b) + (!c  ) = a+b = S0(t=2)
g(0,t=) = offset = a+b+!c = S0 30
Example
g(0,t=2) : the set of input vectors under which
g gets stable to 0 no later than t=2
d
g
a
b e f
Offset:
NOTstabilized by t=2
under abc=000
c
g(0,t=2) = a+b
g(0,t=) = offset = a+b+!c
g(0,t=) \ g(0,t=2) = (a+b+!c) !(a+b) = !a !b !c = satisfiable
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Summary

False-path-aware arrival time analysis is well-

understood
– Practical algorithms exist
• Can handle industrial circuits easily
Remaining problems
– Incremental analysis (make it so that a small change in the
circuit does not make the analysis start all over)
– Integration with logic optimization
– DSM issues such as cross-talk-aware false path analysis

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Timed ATPG
Yet another way to solve the same decision problem

A generalization of regular ATPG:

– regular ATPG
• find an input vector that differentiates a fault-free circuit and a
faulty circuit in terms of functionality
– Timed ATPG
• find an input vector that exhibits a given timed behavior
• Timed extension of PODEM

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