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Unit Iv Reliability and Clock Synchronization

The document discusses techniques for reliability evaluation and clock synchronization in distributed systems. It introduces reliability models for hardware redundancy and algorithms for fault-tolerant clock synchronization. Two clock synchronization architectures are described: a completely connected system with zero propagation delay, and a sparsely connected system also with zero propagation delay. Signal propagation delays and their impact on synchronization are discussed, along with some corrective measures.

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153 views15 pages

Unit Iv Reliability and Clock Synchronization

The document discusses techniques for reliability evaluation and clock synchronization in distributed systems. It introduces reliability models for hardware redundancy and algorithms for fault-tolerant clock synchronization. Two clock synchronization architectures are described: a completely connected system with zero propagation delay, and a sparsely connected system also with zero propagation delay. Signal propagation delays and their impact on synchronization are discussed, along with some corrective measures.

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p.arunagiri
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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UNIT IV

Reliability and Clock Synchronization

Introduction to Reliability Evaluation Techniques -


Reliability Models for Hardware Redundancy –
Permanent faults only - Transient faults.
Introduction to clock synchronization – A Non-
Fault-Tolerant Synchronization Algorithm - Fault-
Tolerant Synchronization in Hardware –
Completely connected zero propagation time
system – Sparse interconnection zero
propagation time system –Fault tolerant analysis
with Signal Propagation delays
COMPLETELY CONNECTED, ZERO
PROPAGATION-TIME SYSTEM
• Every clock is connected by a dedicated
line to ever other clock.
• We assume, to begin with, that signal-
propagation times are zero.
• Each clock has a reference circuit (accept
as input the clock ticks)
• Generates a reference signal to which its
VCO tries to align itself.
•The problem of designing a fault-tolerant synchronizer
thus reduces to obtaining a reference signal that will
permit the system to remain synchronized in the face of
up to a given number of failures.

•To make the reference signal equal to the median of the


incoming signal.

•Unfortunately, this won’t work if there are two or more


maliciously faulty clocks.
Structure of phase locked loop used in synchronization
Structure of phase locked loop used in
synchronization
SPARSE-INTERCONNECTION, ZERO-
PROPAGATION TIMES SYSTEM
• Instead of a completely connected structure,
clocks organized into multiple clusters.
• Each clock in a cluster is connected by a
dedicated link to every other clock in that
cluster.
• pair of clusters
• Assume signal propagation times are zero
• Each clock can run the phase-locked algorithm
SPARSE-INTERCONNECTION, ZERO-
PROPAGATION TIMES SYSTEM
• For every pair of clusters, there will either be a
direct link between two clusters or a link
through a third cluster
SIGNAL PROPAGATION DELAY & CORRECTIVE MEASURES:

• The propagation delay for an integrated circuit


(IC) logic gate may differ for each of the
inputs.
• If all other factors are held constant, the
average propagation delay in a logic gate IC
increases as the complexity of the internal
circuitry increases.
• Some IC technologies have inherently longer tpd values than others,
and are considered "slower.

• Propagation delay is important because it has a direct effect on the


speed at which a digital device, such as a computer, can operate.

• This is true of memory chips as well as microprocessors.


• In a communications system, propagation delay refers to the
time lag between the departure of a signal from the source
and the arrival of the signal at the destination.
• This can range from a few nanoseconds or microseconds in
local area networks (LANs) up to about 0.25 s in
geostationary-satellite communications systems.
• Additional propagation delays can occur as a
result of the time required for packets to make
their way through land-based cables and
nodes of the Internet.
• The propagation delay times in the high-speed
IC logic circuits, triggers, registers, counters
etc. are equal to fractions of a nanosecond and
their measurement is the difficult technical
task.
• For these purposes testers with sampling
converters of the signal time scale are
frequently used.
• During the IC manufacturing the check and
certification of tens of propagation delay
times between several tens inputs and
outputs can be required.
• Usual sampling converters have from two to
four inputs and are usually supplied with
special high-frequency commutator, which
consist of many high-frequency coaxial cables
segments and high frequency, tunable with a
wave resistance of a cable, reed-relays or
mercury relays.
• By the means of a relay commutation of IC
outputs and of a sampling converter inputs is
provided.
• Application of the high-frequency channel
commutator results in the significant
reflections, distortion and, as consequence, in
deterioration of accuracy of measurement.
• The electromagnetic relays considerably
reduce productivity measurement because of
small speed of switching. The measuring
systems of this kind are complex, expensive
and bulky devices.

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