Semiconductor Memories

© Digital Integrated Circuits2nd Memories

Memory

 Differentformats and styles

 Type of the memory is a function of size,
access time, access pattern, application and
system requirements
 Size depends on the abstraction level

© Digital Integrated Circuits2nd Memories

Memory Timing: Definitions
Read cycle

READ

Write cycle
Read access Read access
WRITE

Write access
Data valid

DATA

Data written

• Read access, write access and cycle times

© Digital Integrated Circuits2nd Memories

Semiconductor Memory Classification
(based on functionality, access pattern, nature of storage)

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access (Low production cost)
2
E PROM

SRAM FIFO
Programmable (PROM)
DRAM LIFO (1 time programmable)
FLASH
Shift Register
CAM

© Digital Integrated Circuits2nd Memories

Memory
 Serial memory – video memory
 CAM – uses a word of data itself as input – match flag
 Single port and multiple ports (for higher bandwidth)
Ex : Register file in a RISC uP
 Cost effective technologies – optical and magnetic
disks – extensive storage capabilities
 Slow & limited access patterns
 EPROM – erasable – UV light
 Hybrid devices – EEPROM & FLASH
 EEPROM – slow, costly, byte by byte erasure
 FLASH – fast, low cost, sector by sector erasure

© Digital Integrated Circuits2nd Memories

Memory Architecture: Decoders
M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell

words A K-
N SN- 2 1
Decoder
Word N - 2 Word N - 2
SN - 1
Word N - 1 Word N - 1
K = log2 N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N

© Digital Integrated Circuits2nd Memories

 • Multiple words in a single row
• Works well upto 64 kbits to 256 kbits
• Serious speed degradation
© Digital Integrated Circuits2nd Memories
 Hierarchical Memory Architecture
Block 0 Block i Block P 2 1

Row
address

Column
address
Block
address

Global data bus

Control Block selector Global
circuitry amplifier/driver

I/O
Advantages:
1. Shorter wires within blocks – faster access times
2. Block address activates only 1 block => power savings
© Digital Integrated Circuits2nd Memories
Block Diagram of 4 Mbit SRAM
Clock Z-address X-address
generator buffer buffer
32 blocks
Predecoder and block selector
Bit line load Each 128Kbits
Each block:
1024 rows
128 K Array Block 0
Subglobal row decoder 128 columns
Subglobal rowGlobal
decoder row decoder
Block3130
Block Block 1

Transfer gate
Column decoder
Sense amplifier and write driver
Local row decoder
CS, WE I/O x1/x4 Y-address X-address
buffer buffer controller buffer buffer

© Digital Integrated Circuits2nd [Hirose90] Memories

Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

No physical connection between BL and WL

BL is resistively clamped to ground BL is resistively clamped to vdd

© Digital Integrated Circuits2nd Memories

MOS OR ROM – improved isolation
BL[0] BL[1] BL[2] BL[3]

WL[0]
V DD
WL[1]

WL[2]
V DD

WL[3]

V bias

Pull-down loads
• More complex & larger area
• Pull-up device must be wider than pull-down device
• extra supply contact
© Digital Integrated Circuits2nd Memories
 MOS NOR ROM
V DD
Pull-up devices

WL[0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

© Digital Integrated Circuits2nd Memories

MOS NOR ROM
 Resistance of pull-up device must be larger than
the pull-down resistance to ensure adequate low
level
 To keep the size & BL capacitances small, the
pull-down device must be kept as close as
possible to minimum size.
 As pull-down device width decreases, VOL
increases and Noise margin decreases – tolerable
within the memory core
 Restoration of the full voltage swing is required –
sense amplifier
© Digital Integrated Circuits2nd Memories
MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL[3]

WL [0]

WL [1]

WL [2]

WL [3]

• All word lines high by default with exception of selected row

• All transistors in the pull-down chain must be ON to produce a low value

© Digital Integrated Circuits2nd Memories

MOS NAND ROM
 By default, all WLs are high with the
exception of the selected row
 WL must be operated in reverse logic mode
 Basic cell consists of transistor and no
connection to any of the supply voltage is
needed
 Reduction in the cell size
 All transistors constituting a column are
connected in series

© Digital Integrated Circuits2nd Memories

Equivalent Transient Model for MOS NOR ROM
Model for NOR ROM
V DD
Transient response of memory
Array is the time it takes from
the WL switching until the point BL
when BL has traversed a certain WL
rword
Cbit
Voltage swing, ∆V (typ. Value:
0.5 V cword

 Word line parasitics

 Wire capacitance and gate capacitance
 Wire resistance (polysilicon) – high sheet resistance
 Use of silicided polysilicon is advisable
 Bit line parasitics
 Resistance not dominant (metal - Al)
 Drain and Gate-Drain capacitance

© Digital Integrated Circuits2nd Memories

Equivalent Transient Model for MOS NAND ROM
V DD

Model for NAND ROM

BL

CL
r bit

cbit
r word
WL

cword

 Word line parasitics

 Similar to NOR ROM
 Bit line parasitics
 Resistance of cascaded transistors dominates
 Each of the series transistors can be modeled as a resistance &
capacitance combination - distributed RC network
 Drain/Source and complete gate capacitance

© Digital Integrated Circuits2nd Memories

 Decreasing Word Line Delay
Driver
WL Polysilicon word line

Metal word line

(a) Driving the word line from both sides

Metal bypass

WL K cells Polysilicon word line

(b) Using a metal bypass

(c) Use silicides

© Digital Integrated Circuits2nd Memories

 Disadvantages – NAND & NOR structures
 Ratioed logic – VOL is determined by the
ratio of pull-up & pull-down devices

 Static power dissipation

© Digital Integrated Circuits2nd Memories

Precharged MOS NOR ROM
f V DD
pre

Precharge devices

WL [0]

GND
WL [1]

WL [2]
GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

• PMOS pre-charge device can be made as large as necessary, but clock

driver becomes harder to design
• Every read operation should be followed by a –ve pulse
• Dynamic architecture enables independent control of the pull-up &
pull-down timing

© Digital Integrated Circuits2nd Memories

 Non-Volatile R-W Memories
 Virtually identical to ROM
 An array of transistors placed on a WL/BL grid
 A modified transistor is used which permits its
threshold to be altered
 To reprogram, programmed values must be
erased and new programming round has to be
started
 Method of erasing is the differentiating factor
between various classes of these non-volatile
memory

© Digital Integrated Circuits2nd Memories

Non-Volatile R-W Memories - EPROM
The Floating-gate Avalanche injection MOS
transistor (FAMOS)
Floating gate Gate
D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

• Insertion of extra gate

• Reduced device transconductance and increased threshold voltage

© Digital Integrated Circuits2nd Memories

 Floating-Gate Transistor Programming

20 V 0V 5V

20 V 0V 5V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

© Digital Integrated Circuits2nd Memories

 A “Programmable-Threshold” Transistor

“0”-state “1”-state

“ON ”

DV T

“OFF ”
V WL V GS

© Digital Integrated Circuits2nd Memories

 Floating gate transistor
 ΔVTh = (- ΔQFG) / CFC
 Trapped charge can be stored for many
years even when the supply is removed
- non-volatile memory
 Need for high programming voltages

© Digital Integrated Circuits2nd Memories

EPROM
- Erasable using UV light
- UV light renders the oxide conductive by the
generation of e-h pairs in the material
- Erasure is slow- takes some secs. to minutes
- Limited endurance – a max. of 1000 erase/
program cycles
- Reliability - Device thresholds might vary
- Simple and dense – low cost
- Injection always entails a large channel current
as high as 0.5mA at a control gate voltage of
12.5V- high power dissipation during
programming
- Erasure has to occur “off system”
© Digital Integrated Circuits2nd Memories
EEPROM – FLOTOX (Floating gate tunneling
Oxide)
Floating gate Gate I

Source Drain

20–30 nm -10 V V GD

10 V

n+ n+
Substrate
p
10 nm
Fowler-Nordheim tunneling
I-V characteristic
FLOTOX transistor
- Bidirectionality

© Digital Integrated Circuits2nd Memories

FLOTOX
• Programming is reversible
- erasing is achieved by reversing the voltage
applied during the writing process
• Threshold control problem
• Unprogrammed transistor might be depletion
device
• May result in depletion device if too much charge
from the floating gate is removed
• Threshold Voltage depends on
- initial charge on the gate
- applied programming voltage
- oxide thickness
© Digital Integrated Circuits2nd Memories
EEPROM Cell
BL

WL 2 transistor cell
Transistor is the access
device for read
VDD Flotox performs the storage
function

© Digital Integrated Circuits2nd Memories

EEPROM Cell
 Fabrication of very thin oxide is very
challenging & costly
 Pack less bits at a higher cost
 Offers higher versatility
 Lasts longer – 105 erase/write cycles
 Repeated programming causes a drift in
the threshold voltages due to permanently
trapped charges in SiO2

© Digital Integrated Circuits2nd Memories

Flash EEPROM

Control gate
Floating gate

erasure Thin tunneling oxide

n + source n+ drain
programming
p- substrate

© Digital Integrated Circuits2nd Memories

Flash EEPROM
 Popular nonvolatile memory
 Combines the density of EPROM with the versatility of
EEPROM
 Most Flash devices use the avalanche hot injection
approach to program the device
 Erasure is same as that of EEPROM cells
 Erasure is performed in bulk for the complete chip –
Flash concept
 Extra transistor is eliminated

 The monitoring control hardware on the memory

continuously checks the threshold during erasure &
adjusts the erasure time dynamically.
© Digital Integrated Circuits2nd Memories
Cross-sections of NVM cells

Flash EPROM
© Digital Integrated Circuits2nd Courtesy Intel Memories
 ETOX flash cell
 Resembles FAMOS except that a very thin
tunneling gate oxide is utilized(10nm)
 Different areas of the gate oxide are used
for programming & erasure
 Programming by applying a high voltage
(12V) on the gate & drain for a grounded
source, while erasure occurs with the gate
grounded & source at 12V

© Digital Integrated Circuits2nd Memories

 Basic Operations in a NOR Flash Memory―
Erase
cell array
BL 0 BL 1
G
12 V
0V WL 0
S D

0V WL 1

open open

• All cells are erased simultaneously

© Digital Integrated Circuits2nd Memories
 Basic Operations in a NOR Flash Memory―
Write
12 V BL 0 BL 1
G
6V
12 V WL 0
S D

0V WL 1

6V 0V

• To obtain a threshold shift of 3 to 3.5V, a pulse with typical values

in the range 1-10us must be used
© Digital Integrated Circuits2nd Memories
 Basic Operations in a NOR Flash Memory―
Read
BL 0 BL 1
5V
G
1V
5V WL 0
S D

0V WL 1

1V 0V

© Digital Integrated Circuits2nd Memories

 Flash in NOR architecture
 Leads to fast random read access times
 But erasure & programming are slow
 Most suitable for applications such as
program - code storage
 For large storage density applications
NAND ROM architecture is suitable
(video & audio file storage -- fast erasure,
programming & fast serial access)

© Digital Integrated Circuits2nd Memories

 NAND Flash Memory
Word line(poly)
• Uses Fowler – Nordheim tunneling
for both programming & erasure
• Approx. 40% smaller than the NOR
cell
Unit Cell

Source line
(Diff. Layer)

© Digital Integrated Circuits2nd Courtesy Toshiba Memories

 BL

SL 1
Erasure
BL=SL=12V, all WL=0
Word line(poly) -depletion devices
Programming
SL2 is isolated – no conduction path
SL1 high
To write a 1
Unit Cell BL=0or <10V, WLn=20V->high VT
device
To write a 0
BL=20V, WLn=20V->VT does not
change
Read
SL1=SL2=5V, WLn=5V, BL=5V
RD1 => If any one of the devices has high VT ,
output = 1
SL2 RD0=> If no device in the chain has high VT,
Source line all devices conduct (depletion mode
(Diff. Layer) operation)

© Digital Integrated Circuits2nd Memories

 NAND Flash Memory
Select transistor Word lines

Active area

STI

Bit line contact Source line contact

© Digital Integrated Circuits2nd Courtesy Toshiba Memories

 Characteristics of State-of-the-art NVM

© Digital Integrated Circuits2nd Memories

Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

 DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

© Digital Integrated Circuits2nd Memories

6-transistor CMOS SRAM Cell
WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

• Similar to static SR latch

• Access to the cell is enabled by the WL which replaces the clk
• Dual BLs – storing the signal and it’s inverse- increases NM
© Digital Integrated Circuits2nd Memories
CMOS SRAM Analysis (Read)
WL

V DD
BL M4
BL
Q= 0
Q= 1 M6
M5

V DD M1 V DD V DD

Cbit Cbit

© Digital Integrated Circuits2nd Memories

Boundary constraints on the device sizes can be derived by solving the
Current eqn. at the maximum allowed value of the voltage ripple

© Digital Integrated Circuits2nd Memories

CMOS SRAM Analysis (Read) (0.25um)

1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2[V]
Voltage rise
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)
CR > 1.2

© Digital Integrated Circuits2nd Memories

CMOS SRAM Analysis (Write)
WL
V DD
M4

Q= 0 M6
M5
Q= 1

M1
V DD
BL = 1 BL = 0

© Digital Integrated Circuits2nd Memories

 CMOS SRAM Analysis (Write)

PR = (w4/L4) / (W6/L6) ; PR < 1.8

© Digital Integrated Circuits2nd Memories

 CMOS SRAM analysis
 PR must be less than 1.8
 Lower the PR, lower is the value of VQ
 Tooless a value of PR ends up in problems
 Asymmetric inverters & decreased NM

© Digital Integrated Circuits2nd Memories

 Performance of SRAM cell
 Read requires the (dis)charging of large bit
line capacitance through the stack of 2
transistors
 Write time is dominated by the propagation
delay of the cross coupled inverter pair
 To accelerate the read time, SRAMs use
sense amplifiers which sense the difference
in the voltages on BL & BL

© Digital Integrated Circuits2nd Memories

6T-SRAM — Layout
VDD Substantial area due to devices,
signal routing & connections
M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

© Digital Integrated Circuits2nd Memories

 Resistance-load SRAM Cell (4T SRAM cell)
WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

• Reduces the cell size by approximately one third

• Function of RL is to replenish the charge lost by leakage
• RL can be large to minimize the static power dissipation

© Digital Integrated Circuits2nd Memories

 SRAM Characteristics

© Digital Integrated Circuits2nd Memories

3-Transistor DRAM Cell – refresh (read
followed by write)
BL 1 BL 2

WWL

RWL WWL

M3 RWL

V DD
M1 X
M2
X
- VT
V DD
CS BL 1

BL 2 V DD VT DV

Write : WWL is asserted Read : RWL asserted

BL1 – appropriate data BL2 - high
CS – loaded with data M2 is either off or on

BL2 low when a 1 was stored

Cell is inverting
© Digital Integrated Circuits2nd Memories
 3T DRAM Cell
• Load device/resistance is eliminated- so less complex
• Refresh should occur every 1 to 4ms
• 4T cell stores both data and its complement –
contains redundancy
• In 3T cell, redundancy is eliminated
• This cell is the core of the 1st popular MOS
semiconductor memory – 1Kbit memory from Intel
• No constraints on the device ratios
• Read is nondestructive – data value stored in the cell
is unaltered by a read operation
• Value stored at node X when writing a “1” = VWWL – VTn
-- read access time is increased
---Solution : bootstrap the WL voltage
© Digital Integrated Circuits2nd Memories
3T-DRAM — Layout
BL2 BL1 GND

RWL
M3

M2

WWL
M1

© Digital Integrated Circuits2nd Memories

 1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL (contains data).

Read: BL is precharged to VPRE, WL is asserted
Charge redistribution takes place between bit line capacitance and storage capacitance
CS
V = VBL – V PRE = (VBIT – V PRE)) ------------
C S + CBL
Voltage swing is small; typically around 250 mV.

© Digital Integrated Circuits2nd Memories

DRAM Cell Observations
 1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution based read-out – amplification of
∆V is required
 DRAM memory cells are single ended in contrast to SRAM
cells.
 The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
 Unlike 3T cell, 1T cell requires presence of an extra
capacitance (Cs) that must be explicitly included in the design.
 When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

© Digital Integrated Circuits2nd Memories

 Sense Amp Operation

V BL V(1)

V PRE
ΔV

V(0)
Sense amp activated t
Word line activated

© Digital Integrated Circuits2nd Memories

1T DRAM Cell
 Voltage change is around 250mV for the state of
the art memories
 Cs/(Cs+CBL) – Charge transfer ratio and ranges
between 1% to 10%
 Minimum capacitance value is 30fF. Fitting this
large capacitance in as small an area as possible
is the key challenges in DRAM designs
 If ΔV is positive, logic high is read and if ΔV is
negative, logic low is read

© Digital Integrated Circuits2nd Memories

 Static CAM Memory Cell
Bit Bit Bit Bit
Word Bit Bit
M8 M9
M4 M5
CAM ••• CAM
M6 M7

Word ••• •••

Word S S
int
CAM ••• CAM M3 M2
Match
M1

Wired OR Match Line

© Digital Integrated Circuits2nd Memories

 CAM in Cache Memory

CAM SRAM
ARRAY ARRAY
Hit Logic

Address Decoder

Input Drivers Sense Amps / Input Drivers

Address Tag Hit R/W Data

© Digital Integrated Circuits2nd Memories

 CAM in cache memory
 Cache is small, fast, stores a small fraction of
overall memory and is placed between the
processor and large dense main memory
(DRAM)
 Works on the principle of spatial and temporal
data locality
 Consists of 2 parts – CAM array (addresses)
and SRAM array (data)

© Digital Integrated Circuits2nd Memories

 Periphery

 Address Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry

© Digital Integrated Circuits2nd Memories

 Row Decoders
Collection of 2M complex, M input logic gates
Organized in regular and dense fashion
(N)AND Decoder

Each WL : 16 transistors
Total of 4096 transistors

NOR Decoder

© Digital Integrated Circuits2nd Memories

 Issues

• Area is more
• Large fan-in - negative impact on performance
• NOR gate has to drive large load presented by the WL
while not overloading the input
• Power dissipation has to be kept in check

Static & Dynamic decoder design

• Static CMOS vs. Pseudo NMOS

© Digital Integrated Circuits2nd Memories

Hierarchical Decoders (static type)
Splitting a complex gate into 2 or more logic layers.
Multi-stage implementation improves performance
•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••

NAND decoder using

A1 A0 A0 A1 A3 A2 A2 A3 2-input pre-decoders

No. of transistors : 256x8 + 64

© Digital Integrated Circuits2nd Memories
 Issues

• Number of transistors is less

• As the number of inputs to NAND gates is halved,
the propagation delay is reduced by approx. a
factor of 4
• Still , a 4 input NAND gate is present – large load
• beneficial to have more stages of logic – say 2 input
NANDs, 2 input NORs & inverters

© Digital Integrated Circuits2nd Memories

Dynamic Decoders

Precharge devices GND GND VDD

WL3
VDD
WL 3

WL 2
WL 2 VDD

WL 1
WL 1
V DD
WL 0
WL 0

VDD  A0 A0 A1 A1
A0 A0 A1 A1 

2-input NOR decoder 2-input NAND decoder

When both A0&A1 = 0 When both A0&A1 = 1
WL0 is high WL0 is low (selected)
© Digital Integrated Circuits2nd Memories
NOR & NAND decoders
 Active low signalling in NAND is in
correspondence with the WL
requirements of NAND ROM
 NAND decoder is slower
 NOR decoder consumes more area and
more power

© Digital Integrated Circuits2nd Memories

4-input pass-transistor based column
decoder
BL 0 BL 1 BL 2 BL 3

S0
A0
S1

S2

A1 S3

2-input NOR decoder

D
Read
Provide discharge path from precharged bitlines to SA
Write
Must be able to drive the BL low to write a 0

© Digital Integrated Circuits2nd Memories

 Column decoder
Advantage: speed
-- only one extra transistor in signal
path
Disadvantage: Large transistor count

© Digital Integrated Circuits2nd Memories

4-to-1 tree based column decoder
BL 0 BL 1 BL 2 BL 3

A0

A0

A1

A1

• No pre-decoder is required

© Digital Integrated Circuits2nd Memories

Tree decoder
 Number of devices drastically reduced
 A chain of K series connected pass transistors
in the signal path.
 Delay increases quadratically with # of sections;
prohibitively slow for large decoders
 Solutions
--- Buffers
--- Progressive sizing of transistors
--- combination of tree and pass transistor
approaches

© Digital Integrated Circuits2nd Memories

Sense Amplifiers - Analog circuits
make V as small
C  V as possible
tp = ----------------
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

© Digital Integrated Circuits2nd Memories

 Functions of Sense Amplifier

• Amplification – bitline swing is small (typ. 100mV)

• Delay reduction - compensates for the restricted
fan-out driving capability of the
memory cell by accelerating the BL
transition
• Power reduction – reduction in the signal swing on the
BL reduces the power dissipation
related to charging & discharging of
BLs.
• Signal restoration – After every read, refresh of BL is to
be done

Topology of SA is a function of type of memory device,

Voltage levels and overall memory architecture
© Digital Integrated Circuits2nd Memories
Differential Sense Amplifier
V DD

M3 M4
y Out

bit M1 M2 bit

SE M5
Directly applicable to
SRAMs

Common noise voltages and spikes on power supply are suppressed

© Digital Integrated Circuits2nd Memories

Differential Sensing ― SRAM

• The BL and BL signals are heavily loaded by large BL

capacitances – BL swing is small
•The amplifier is conditioned by the SA enable signal
• Initially, inputs are precharged and equalised to a
common value, while SE is low, disabling the sensing
circuit.
• Once read is initiated (WL is asserted), one of the BLs
drops
• SE is enabled when a sufficient differential signal has
been established and the amplifier evaluates.

© Digital Integrated Circuits2nd Memories

 Differential Sensing ― SRAM
V DD V DD
PC

BL BL V DD V DD
EQ
M3 M4

WL i
x M1 M2 2x x 2x

SE M5 SE

SE
SRAM cell i

V DD
Diff.
x Sense 2x Output
Amp

SE
Output
(a) SRAM sensing scheme (b) two stage differential amplifier

© Digital Integrated Circuits2nd Memories

Differential Sensing ― SRAM
• BLs are precharged to VDD by pulling PC low
• PC transistor is ON ensuring the initial voltages
on both BLs are identical – Equalization
• Read operation is started by disabling the precharge
& Equalization devices & enabling one of WLs. One of
BLs is pulled low by the selected memory cell
• Grounded PMOS load limits the BL swing and speeds
up the next precharge cycle
• Once a sufficient signal is built up (typ.0.5V), the SA
is turned on by raising SE. Differential input signal
is amplified & a rail to rail output is produced at the
output of the inverter.
• BL swing is determined by the SRAM cells & static PMOS
load
© Digital Integrated Circuits2nd Memories
 Latch-Based Sense Amplifier
EQ
BL BL
VDD

SE

SE

Initialized in its meta-stable point with EQ (by equalising the BLs)

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.

© Digital Integrated Circuits2nd Memories

 Charge-Redistribution Amplifier
V ref

VL VS
M1

C small
M2 M3 Clarge

Transient Response
2.5

Concept 2.0 VS
V in
1.5

V
VL
1.0

0.5
Vref
V ref=53V
3V
0.0
0.0 1.00 2.00 3.00
time (nsec)

© Digital Integrated Circuits2nd (b) Transient responseMemories

 Charge-Redistribution Amplifier―
EPROM V DD

SE M4 Load
Out

Cout Cascode
V casc M3 device

Ccol
Column
WLC M2 decoder

BL
M1 CBL EPROM
WL array

© Digital Integrated Circuits2nd Memories

 Single-to-Differential Conversion
WL
BL 2x
x
Diff.
1
Cell S.A. 2
V ref

Output

© Digital Integrated Circuits2nd Memories

 Open bit-line architecture with
dummy cells (1TDRAM)
EQ

L L1 L0 V DD R0 R1 L
SE

BLL BLR

… …
CS CS CS CS CS CS
SE

Dummy cell Dummy cell

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 DRAM Read Process with Dummy Cell
3 3

2 2

BL BL

1 V V 1
BL BL

0 0
0 1 2 3 0 1 2 3
t (ns) t (ns)

reading 0 reading 1
3
EQ WL

SE
V
1

0
0 1 2 3
t (ns)

control signals
© Digital Integrated Circuits2nd Memories
Open bitline architecture with
dummy cells (1TDRAM)
• When EQ is raised, BLL=BLR=VDD/2
• Enabling L & L ensures that dummy cells are charged to Vdd/2
• During read, one of the WLs (say left side) is enabled causing a
voltage change on BLL
• Simultaneously select the dummy cell on the other half
• The sense latch toggles depending on the voltage difference
• Perfect symmetry is important
• Capacitive coupling between BL and WL effectively eliminated
by the sense amplifier
• BL capacitance is reduced by dividing the memory array
• Charge transfer ratio increases
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 Voltage References
• Boosted WL voltage – above VDD
• Half VDD
• Reduced internal supply
• Negative substrate bias – to control the threshold
voltages

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Voltage Regulator

VDD

Mdrive
VREF VDL
Equivalent Model
Vbias
VREF
-
Mdrive
+

VDL

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 Voltage regulator

• Used to create a low internal supplies, allowing the

interface circuits to operate at higher voltages

• Uses a large PMOS output driver transistor to drive

the load of the memory circuit

• Uses a –ve feedback to set the output to the ref.

voltage and immune to changes

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 Charge Pump – WL boosting
V DD
2V DD 2- V T
VB
M1
V DD 2- V T
CLK A B
0V
C pump
M2
V load
C load V load

0V

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 Charge Pump
• Provides Voltage sources that exceed the supply but does
not draw much current
• Transistors M1 & M2 are connected in diode style
• When clk is high, A is ground & B is at VDD-VT
• The charge stored in the capacitor
Q = Cpump (VDD-VT)
• When clk is low, A=VDD, B rises, M1 shuts off
• When B is one threshold above Vload , M2 starts conducting,
charge is transferred to Cload
• During consecutive clk cycles, pump continues to
deliver charge to Vload until 2(VDD-VT)
• The amount of current drawn from the generator
is determined by capacitor’s size & clk frequency

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Semiconductor Memory Trends
(up to the 90’s)

Memory Size as a function of time: x 4 every three years

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Semiconductor Memory Trends (updated)

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