Module 1 : Architecture
Digital Signal Controller
TMS320F2812
Texas Instruments Incorporated
European Customer Training Center
University of Applied Sciences Zwickau (FH)
1-1
C281x Block Diagram
Program Bus Event
Event
Manager
ManagerAA
Boot Event
Event
Boot Manager
Sectored
Sectored ManagerBB
RAM ROM
ROM
Flash RAM
22 Flash 12-bit
12-bitADC
ADC
A(18-0)
32 Watchdog
Watchdog
32
D(15-0)
32 McBSP
PIE McBSP
32-bit R-M-W
R-M-W Interrupt
32-bit 32x32 bit Manager CAN2.0B
CAN2.0B
Auxiliary 32x32 bit Atomic
Auxiliary
Multiplier Atomic
Registers Multiplier ALU SCI-A
Registers ALU SCI-A
33
32 SCI-B
Realtime 32bit
bit SCI-B
Realtime Register Bus Timers
Timers SPI
JTAG
JTAG CPU SPI
Data Bus GPIO
GPIO
1-2
C28x CPU
MCU/DSP balancing code
density & execution time.
Supports 32-bit instructions
Program Bus for improved execution time;
Supports 16-bit instructions
for improved code efficiency
32-bit fixed-point DSP
PIE
32-bit
32-bit 32x32 bit R-M-W
R-M-W Interrupt 32 x 32 bit fixed-point MAC
32x32 bit Manager
Auxiliary
Auxiliary Multiplier Atomic
Atomic
Multiplier
Dual 16 x 16 single-cycle fixed-
Registers
Registers ALU
ALU point MAC (DMAC)
33
32
32bit
bit
32-/64-bit saturation
Register Bus Timers
Realtime
Realtime Timers 64/32 and 32/32 modulus division
CPU
JTAG
JTAG Fast interrupt service time
Data Bus Single cycle read-modify-write
instructions
Unique real-time debugging
capabilities
Upward code compatibility
1-3
C28x Multiplier and ALU / Shifters
Program Bus
32
Data Bus
XT (32) or T/TL 16/32
16 8/16/32
MULTIPLIER
32 32 x 32 or
Shift R/L (0-16) Dual 16 x 16
P (32) or PH/PL 8/16
32
32
32
32 Shift R/L (0-16)
32
ALU (32)
32
ACC (32)
AH (16) AL (16)
[Link] [Link] [Link] [Link]
• 32
Shift R/L (0-16)
32
Data Bus
1-4
C28x Pointer, DP and Memory
Data Bus
Program Bus
6 LSB
XAR0 DP (16) from IR
XAR1
XAR2
32 22
XAR3
XAR4 MUX
XAR5
XAR6
XAR7 MUX
ARAU
Data Memory
XARn 32-bits
ARn 16-bits
1-5
C28x Internal Bus Structure
Program Program Address Bus (22)
PC Program
Program-read Data Bus (32)
Decoder (4M* 16)
Data-read Address Bus (32)
Data-read Data Bus (32) Data
(4G * 16)
Registers Execution Debug
ARAU MPY32x32 Memory
Real-Time
SP R-M-W Emulation
ALU
DP @X Atomic &
XT JTAG
XAR0 ALU Test Standard
to P
ACC Engine Peripherals
XAR7
Register Bus / Result Bus External
Interfaces
Data/Program-write Data Bus (32)
Data-write Address Bus (32)
1-6
C28x Atomic Read/Modify/Write
Atomic Instructions
Benefits:
LOAD
READ Simpler programming
Registers CPU ALU / MPY Mem Smaller, faster code
WRITE
Uninterruptible (Atomic)
STORE
More efficient compiler
Standard Load/Store Atomic Read/Modify/Write
DINT
AND *XAR2,#1234h
MOV AL,*XAR2
AND AL,#1234h 2 words / 1 cycles
MOV *XAR2,AL
EINT
6 words / 6 cycles
1-7
C28x Pipeline
A F1 F2 D1 D2 R1 R2 X W 8-stage pipeline
B F1 F2 D1 D2 R1 R2 X W
C F1 F2 D1 D2 R1 R2 X W
D F1 F2 D1 D2 R1 R2 X W
E & G Access
E F1 F 2 D 1 D 2 R 1 R 2 X W same address
F F1 F 2 D 1 D 2 R 1 R 2 X W
G F1 F2 D1 D2 RR1 1 R2 X WW
R2 X
H F1 F2 D1 DD2 2 R1 RR
2 1 X
WW
R2 X
F1: Instruction Address
F2: Instruction Content Protected Pipeline
D1: Decode Instruction
D2: Resolve Operand Addr Order of results are as written in
R1: Operand Address source code
R2: Get Operand
X: CPU doing “real” work
Programmer need not worry about
W: store content to memory the pipeline
1-8
TMS320F2812 Memory Map
Data | Program Data | Program
0x00 0000 MO SARAM (1K)
0x00 0400 M1 SARAM (1K)
0x00 0800 PF 0 (2K) reserved reserved
0x00 0D00 PIE vector
(256) reserved
ENPIE=1 XINT Zone 0 (8K) 0x00 2000
0x00 1000 reserved
0x00 6000 PF 2 (4K) reserved XINT Zone 1 (8K) 0x00 4000
0x00 7000 PF 1 (4K) reserved
0x00 8000 LO SARAM (4K) reserved
0x00 9000 L1 SARAM (4K)
XINT Zone 2 (0.5M) 0x08 0000
0x00 A000 reserved
XINT Zone 6 (0.5M) 0x10 0000
0x3D 7800 OTP (1K)
0x3D 7C00 reserved 0x18 0000
0x3D 8000 FLASH (128K)
reserved
128-Bit Password
0x3F 8000 HO SARAM (8K)
0x3F A000 reserved
0x3F F000 Boot ROM (4K) XINT Zone 7 (16K) 0x3F C000
MP/MC=0 MP/MC=1
CSM: LO, L1
0x3F FFC0 BROM vector (32) XINT Vector-RAM (32)
MP/MC=0 ENPIE=0 MP/MC=1 ENPIE=0 OTP, FLASH
1-9
Code Security Module
Prevents reverse engineering and
protects valuable intellectual property
0x00 8000 LO SARAM (4K)
0x00 9000 L1 SARAM (4K)
0x00 A000 reserved
0x3D 7800 OTP (1K)
0x3D 7C00 reserved
0x3D 8000 FLASH (128K)
128-Bit Password
128-bit user defined password is stored in Flash
128-bits = 2128 = 3.4 x 1038 possible passwords
To try 1 password every 2 cycles at 150 MHz, it
would take at least 1.4 x 1023 years to try all
possible combinations!
1 - 10
C28x Fast Interrupt Response Manager
96 dedicated PIE
vectors
No software decision
making required PIE module 28x CPU Interrupt logic
Peripheral Interrupts 12x8 = 96
For 96
Direct access to RAM interrupts
vectors INT1 to
INT12 28x
Auto flags update 96
IFR IER INTM CPU
12 interrupts
Concurrent auto PIE
Register
context save
Map
Auto Context Save
T ST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)
1 - 11
C28x / C24x Modes
Mode Type Mode Bits Compiler
OBJMODE AMODE Option
C24x Mode 1 1 -v28 -m20
C28x Mode 1 0 -v28
Test Mode (default) 0 0 -v27
Reserved 0 1
C24x source-compatible mode:
Allows you to run C24x source code which has been reassembled
using the C28x code generation tools (need new vectors)
C28x mode:
Can take advantage of all the C28x native features
1 - 12
Reset – Bootloader
Reset
OBJMODE=0 AMODE=0
ENPIE=0 VMAP=1
XMPNMC=0 Bootloader sets
(microcomputer mode) OBJMODE = 1
AMODE = 0
Reset vector fetched
from boot ROM Boot determined by
state of GPIO pins
0x3F FFC0
Execution
Entry Point
Note: H0 SARAM
Details of the various boot options will be
discussed in the Reset and Interrupts module
1 - 13
Summary
High performance 32-bit DSP
32 x 32 bit or dual 16 x 16 bit MAC
Atomic read-modify-write instructions
8-stage fully protected pipeline
Fast interrupt response manager
128Kw on-chip flash memory
Code security module (CSM)
Two event managers
12-bit ADC module
56 shared GPIO pins
Watchdog timer
Communications peripherals
1 - 14
