ĐẠI HỌC QUỐC GIA TP.

HỒ CHÍ MINH
ĐẠI HỌC BÁCH KHOA
NGÀNH KỸ THUẬT ĐIỆN TỬ

CHƯƠNG 4

KHUẾCH ĐẠI ĐA TẦNG,

KHUẾCH ĐẠI VI SAI
Hoàng Trang
Bộ môn Kỹ Thuật Điện Tử
[email protected]

1
TP.Hồ Chí Minh 03/ 2014
 Overview

Review
In this lecture, at first, we study the low-frequency behavior of
multi-stage CMOS amplifiers. Analyzing operation model and
characteristics of each circuit. Then, we discuss about
differential pair circuit in order to amplify the differential signal.
Analyzing the behavior in both large signal and small signal
model. We develop intuitive techniques and models that prove
useful in understanding more complex systems

Following a brief review of basic concepts, we describe in this

chapter two types of amplifiers:
• Multi-stages Amplifier.
• Differential Amplifier.

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 Outline

0. Introduction

1. Multistage Amplifier.

2. Differential Amplifier.

3. Sumary

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 Outline

0. Introduction

1. Multistage Amplifier.

2. Differential Amplifier.

3. Sumary

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 1. Multistage Amplifer

Most often, single stage amplifier does not accomplish design goals:

• Need more gain than could be provided by a single stage

• Need to adapt to specified RS and RL to maximize efficiency

Multistage Amplifier

• What amplifying stages should be used and in what order?

• What devices should be used, BJT or MOSFET?

• How is biasing to be done?

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 1. Multistage Amplifer
Multistage Amplifier
Table of Content

1.1. Super Source Follower

1.2. Cascade Amplifier.

1.3. Cascode Amplifer.

1.4. Push-Pull Amplifer.

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 1.1. Super Source Follower
Basic Ideas
The source follower circuit is used as a
voltage buffer and level shifter. It is more
flexible level shifter as the dc value of voltage
level can be adjusted by changing aspect
ratio of MOSFETs.

CMOS have much

low transconductance
Output resistance may be too high for some applications, especially when
a resistive load must be driven

• Increase the transconductance base the CMOS W/L

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 1.1. Super Source Follower
DC Analysis
If Vin = Const , Vout increase

Vsg1 = Vin – Vout Decrease

|Id1| ~ (Vsg1 – Vth)^2 so Id1 increase

The M2 Gate-Source Voltage Increase

 Id2 Increase
Negative
 Use the Kirchoff Current Law (KVL) for the
feedback
through M2 output node, the increase of total current tend
to the decrease of the resistance output.

I1 > I2 because of the bias current in M2 is the difference between I1

and I2

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 1.1. Super Source Follower
AC Analysis
Recall the output resistance of current sources are r1 and r2

Shorted Input,
Norton Equivatlent

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 1.1. Super Source Follower
AC Analysis

Assume that current sources are ideal so we can ignore r1 and r2

Output resistance was reduced

To find the small signal gain,

Open the output.

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 1.1. Super Source Follower
AC Analysis
From KCL at the drain of M1

Ideal current sources

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 1.1. Super Source Follower
Application

[Leon Fay, Vinith Misra, and Rahul Sarpeshkar]

Electrocardiogram amplifier schematic.

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 1.1. Super Source Follower
AC Analysis

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 1. Multistage Amplifer
Multistage Amplifier
Table of Content

1.1. Basic Theory

1.2. Cascade Amplifier.

1.3. Cascode Amplifer.

1.4. Push-Pull Amplifer.

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 1.2. Cascade Amplifier
Two-port Network Algebra
In a cascade connection,
• V1 of network X2= V2 of network X1
• I1 of network X2= -I2 of network X1

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 1.2. Cascade Amplifier
Cascade Analysis

A cascade of 2 amplifiers has gains:

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 1.2. Cascade Amplifier
Cascade Analysis
Multistage amplifiers are difficult to compute if the components are not unilateral.
For unilateral amplifiers things are simple. We multiply gains with appropriate
voltage dividers

For non-unilateral amplifiers:

• The input impedance of each stage depends on the input impedance of
the next stage
• The output impedance of each stage depends on the output impedance
of the preceding stage.

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 1.2. Cascade Amplifier
Input - output impedance
Calculate the input impedance of a voltage amplifier driving a load ZL

A similar calculation for the output impedance of a voltage amplifier driven

by a finite impedance Thevenin source ZS gives:

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 1.2. Cascade Amplifier
Voltage Gain

We start with the amplifier After some algebra we conclude that:

definition, use the KCL

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 1.2. Cascade Amplifier
CD-CS cascade configuration

DC gain of the cascade amplifier will be

slightly lower compared with the CS
amplifier

The equivalent input resistance of such

configuration is greatly reduced by gmro
when compared with CS amplifier

The effective time constant is significantly reduced and the

bandwidth can is extended.

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 1.2. Cascade Amplifier
CD-CS cascade configuration
Schematic diagram of TIA
More current are allocated to the
CS stage of the CD-CS cascade in
order to obtain higher amount of
overall gain. To alleviate the
bandwidth reduction by the higher
amount of gain inductive shunt-
peaking technique has been
applied using a novel active
inductor load.

The combination of CD-CS is widely

used for wideband amplifier. As the
cascade of these two amplifiers
reduce the input capacitance while
[Yong-Hun Oh, Sang-Gug Lee, H. H. Park] providing low impedance at the gate
node of CS amplifier.

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 1.2. Cascade Amplifier
CD-CG amplifier

The analysis of the differential amplifier

can be thought as the superposition of
the M1-M2 pair (CD-CG) and M2 (CS
amplifier).

Hence the gain of the differential

amplifier can be derived as gmro.

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 1.2. Cascade Amplifier
Sumary
• The behaviour of BJT and FET configurations is very similar, except for the
difference on the input side of the small signal equivalent circuit.
• A very useful possibility opens up: Use a FET for one stage and a BJT for the other. Mixed bipolar-FET
two-stage combinations try to exploit the smaller input admittance of FETs and the better frequency
response and power handling capability of bipolars at the same time.
• This approach gives rise to the “BiCMOS” manufacturing technologies which use FETs for input stages
and BJTs for output stages, especially line drivers.

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 1. Multistage Amplifer
Multistage Amplifier
Table of Content

1.1. Basic Theory

1.2. Cascade Amplifier.

1.3. Cascode Amplifer.

1.4. Push-Pull Amplifer.

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 1.3. Cascode Amplifier
Cascode Amplifier
Table of Content

1.3.1. Simple Cascode.

1.3.2. Multi-level Cascode.

1.3.3. Folded Cascode.

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 1.3.1 Simple Cascode

DC Analysis

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 1.3.1 Simple Cascode

AC Analysis

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 1.3.1 Simple Cascode

AC Analysis

Transconductance

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 1.3. Cascode Amplifier
Cascode Amplifier
Table of Content

1.3.1. Simple Cascode.

1.3.2. Multi-level Cascode.

1.3.3. Folded Cascode.

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 1.3.2 Multi-level cascode amplifier

Triple cascode amplifie

Cascoding can be extended to three or more stacked

devices to achieve a higheroutput impedance, but the
required additional voltage headroom makes such
configurations less attractive.

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 1.3.2 Multi-level cascode amplifier

NMOS cascode amplifier with PMOS cascode load

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 1.3. Cascode Amplifier
Cascode Amplifier
Table of Content

1.3.1. Simple Cascode.

1.3.2. Multi-level Cascode.

1.3.3. Folded Cascode.

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 1.3.3 Folded Cascode

Architecture

Simple folded cascode Folded cascode with Folded cascode with

proper biasing NMOS input

Why choose folded-cascode amplifier instead of telescopic configuration?

– More freedom to choose the DC input voltage at Vin

– Convenience in shorting the input and the output in feedback configurations.

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 1.3.3 Folded Cascode

Analysis

I1 is the current flowing through M3 and is equal to the sum of ID1and ID2.

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 1. Multistage Amplifer
Multistage Amplifier
Table of Content

1.1. Basic Theory

1.2. Cascade Amplifier.

1.3. Cascode Amplifer.

1.4. Push-Pull Amplifer.

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 1.4 Push-Pull Amplifier

Basic Ideas
Active Load CMOS Inverter Output Swing Limits

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 1.4 Push-Pull Amplifier

The Inverter
Very large signal swing.Not all in linear region

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 1.4 Push-Pull Amplifier

DC Analysis

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 1.4 Push-Pull Amplifier

AC Analysis
Small-signal analysis gives the following results

High gain!

OpAmp/Comparator
Output Buffer

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 1. Multistage Amplifer
BiCMOS multistage voltage amplifier
CAPACITIVE COUPLING
Capacitors that have large enough value behave as AC
short, so the signal goes through but bias is independent
for each stage
• Advantages
– Can select bias point for optimum operation
– Can select bias point close to the mid-point
of the
power rails for maximum voltage swing
• Disadvantages
– To approximate AC short, large capacitors
are needed
and they consume large area.

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 Outline

0. Introduction

1. Multistage Amplifier.

2. Differential Amplifier.

3. Sumary

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 2. Differential Amplifer
Single-End versus Differential Signal
A single-ended signal is measured with respect to a fixed potential (ground)
• A differential signal is measured between two equal and opposite signals
which swing around a fixed potential (common-mode level)
• You can decompose differential signals into a differential mode (difference)
and a common-mode (average)

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 2. Differential Amplifer
Single-End versus Differential Signal
• A single-ended signal is measured with respect to a fixed potential (ground)
• A differential signal is measured between two equal and opposite signals
which swing around a fixed potential (common-mode level)
• You can decompose differential signals into a differential mode (difference)
and a common-mode (average)

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 2. Differential Amplifer
Differrential Signal Advantages
The differential pair (differential amplifier) configuration

The CMOS differential pair

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 2. Differential Amplifer
Differrential Pair

An improved differential amplifier topology utilizes a “tail”

current source to keep the transistor bias current ideally
constant over the common-mode input range

Allows for a constant small-signal gain and output commonmode level

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 2. Differential Amplifer
Differrential Mode Input/Ouput Characteristic

For large-signal differential inputs, the maximum output levels are well
defined and ideally independent of the input common-mod
For small-signal differential inputs, the small-signal gain is maximum
at low-input signal levels
The differential input level increases, the circuit becomes more
nonlinear and the gain decreases

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 2. Differential Amplifer
I/V Characteristic

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 2. Differential Amplifer
I/V Characteristic

The differential current is an odd

function of the differential input
voltage which increases linearly for
small inputs
• For large differential input
voltages, the output differential
current compresses due to the sqrt
term
• The differential output current
maxes out when all the current
flows through one transistor at 'Vin1

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 2. Differential Amplifer
Transconductance

The differential pair

transconductance and
gain is maximum near
zero input differential
voltage

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 2. Differential Amplifer
Small-Signal Analysis
Method 1 Superposition

The X output from Vin1 is

modeled as a degenerated
CS amplifier

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 2. Differential Amplifer
Small-Signal Analysis
Method 1 Superposition

The Y output from Vin1 is

modeled as a Thevenin
equivalent driving a CG
amplifier

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 2. Differential Amplifer
Small-Signal Analysis
Method 1 Superposition

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 2. Differential Amplifer
Small-Signal Analysis
Method 2 Half Circuit Model

• The symmetric differential pair can be modeled as aThevenin

equivalent to observe how the tail node P changes with the
differential input signal
• If RT1=RT2and the input is a truly differential signal, node P
remains constant
• This allows the tail node to be treated as a “virtual ground

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 2. Differential Amplifer
Small-Signal Analysis
Method 2 Half Circuit Model
Applying the virtual ground concept allows modelingas two “half circuits”

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 2. Differential Amplifer
Common Mode I/V Characteristic

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 2. Differential Amplifer
Common Mode Small Signal Analysis

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 2. Differential Amplifer
Common Mode Small Signal Analysis

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 2. Differential Amplifer
Common Mode Small Signal Analysis

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 2. Differential Amplifer
Common Mode Mismatch

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 References

[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

2nd Edition, Oxford Univeristy Press, 2002.

[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

International Edition, Electrical and Computer Engineering Series,
McGraw-Hill, 2001

[3] R. Jacob Baker. "CMOS Circuit Design, Layout, and Simulation", 3rd
Edition, IEEE Press Series on Microelectronic Systems, A Join Wiley &
Son, 2010 .

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