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Architecture of 8051 Microcontroller: Microcontrollers

The 8051 microcontroller has an 8-bit CPU with registers A and B, internal ROM of 4KB, and internal RAM of 128 bytes. It has 32 I/O pins organized into four 8-bit ports, two 16-bit timers, and supports interrupts. The oscillator circuit provides a clock signal in the range of 1-16MHz to synchronize internal operations. The program counter and data pointer are 16-bits wide and are used to access code and data from internal and external memory. The stack pointer manages an internal RAM area used as a stack.

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535 views22 pages

Architecture of 8051 Microcontroller: Microcontrollers

The 8051 microcontroller has an 8-bit CPU with registers A and B, internal ROM of 4KB, and internal RAM of 128 bytes. It has 32 I/O pins organized into four 8-bit ports, two 16-bit timers, and supports interrupts. The oscillator circuit provides a clock signal in the range of 1-16MHz to synchronize internal operations. The program counter and data pointer are 16-bits wide and are used to access code and data from internal and external memory. The stack pointer manages an internal RAM area used as a stack.

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Architecture of 8051

Microcontroller
MICROCONTROLLERS
8051
Architecture of 8051
The 8051 Architecture consist of these
specific features
 The 8 bit CPU with Registers A and B
 Internal ROM (4Kb)
 16-bit program counter(PC) and data pointer(DPTR)
 Internal RAM of 128 bytes:
 Four Register Banks, each containing eight bit registers
 Sixteen bytes which might addressed at bit level
 Eighty bytes of general-purpose data memory
 8-bit Program Status word(PSW)
Two 16 bit Counter / timers: T0,T1
32 input/output pins [4 eight-bit ports P0-P3]
3 internal interrupt and 2 external interrupt
sources.
Control registers: TCON,TMOD,SCON,PCON,IP,IE
Full Duplex Data Transmitter and Reciever: SBUF
Oscillator and clock circuits.
The 8051 oscillator and clock
Clock pulses are used synchronization of internal
operations.
XTAL1 and XTAL2 are provided for connecting a
resonant network from an oscillator.
Typically a Quartz crystal and capacitors are
employed.
Frequency range: 1-16MHz.
Some internal memories are dynamic and must
operate above a minimum frequency or data will be
lost.
Ceramic resonators have low cost, but poor freq
stability and accuracy.
Oscillator circuit and timing
The 8051 oscillator and clock
 f: Clock frequency, P: Pulse Time (Minimum interval of
time).
A machine cycle is minimum amount time must take by
simplest machine instruction.
An 8051 machine cycle is made up of six states.
A state is the basic time interval for discrete operations
of the MC such as fetching opcode byte, decoding an
opcode, executing an opcode, or writing a data byte.
Program instructions may require one or two or four
machine cycles to be executed, depending on the type
of instruction.
• Instructions are fetched and executed by the MC
automatically beginning from 0000h of ROM.
• Time required for any instruction:
Tinst=Cx12d/Crystal Freq;
C- Number of cycles
Example:
For ADD A,R1 C=1. If crystal freq=16MHz
Tinst= 0.75 mirco seconds.
• ALE- Timing pulse for external memory access.
• Two bytes can be fetched and executed in one
machine cycle.
• Single byte instructions will throw away
second byte for first byte next instruction.
Program counter (PC)
 The program counter points to the address of the next
instruction to be Executed

As the CPU fetches the opcode from the program ROM,the
program counter is increasing to point to the next instruction.

 The program counter is 16 bits wide

 This means that it can access program addresses 0000


to FFFFH, a total of 64K bytes of code.
Internal ROM: 0000H to 0FFFH
External for 0FFFH above or totally external for all addresses
0000H to FFFFH.
 PC is automatically incremented after every instruction byte is
fetched and may also be altered by certain instructions.
PC doesn’t have internal address.
Data pointer (DPTR)
 The data pointer is 16 bit register. (two 8 bit registers
DPH and DPL).

It is used to hold the memory addresses for


internal and external code access and external data
access.

DPTR is under the control of program instructions and


can be specified by its name DPTR (16-bit) or by DPH
and DPL (8-bit).
A and B CPU Registers
• The 8051 contains 34 general purpose or working registers.
Two of these Register A and B.
• Hold results of many instructions (Math and logical
operations)

• A- Addition, Subtraction, Integer Multiplication and division,


Boolean bit manipulations. It is also used for data transfer
between 8051 and external memory.

• The B register is used with A for multiplication and division


operation and has no function other than as a location
where data may be stored.
Flags and Program status
word(PSW)
Flags are 1-bit registers provided to store the results
of certain program instructions
Other instructions can test the condition of flags and
make decisions based on the flag states.
They are grouped inside the PSW and PCON
registers.
The 8051 has 4 math flags and 3 general purpose
user flags that can be set to1 or cleared by the
programmer as desired.
Flags and Program status word(PSW)

The math flags include carry(C),auxiliary


carry(AC), overflow(OV) and parity(P).
User flags are named F0,GF0,GF1 used
to record some event in the program.
PSW contains the math flags, F0 and
register select bits.
GF0 and GF1 are stored in PCON.
Program Status Word (PSW)
Internal memory
 ROM- for program code bytes
 RAM- for variable data. (altered when program
runs)
 128 bytes of RAM. (00 to 7F hexadecimal).
 Additional memory can be added externally.
 8051 has a Harvard architecture, which uses the
same address in different memories for code and
data.
 Internal circuitry accesses the correct memory
based on the nature of the operation in progress.
Internal RAM
The 128 byte internal RAM shown in figure
It is organized into three areas.

1.Working register:
Thirty-two bytes from address 00h to 1Fh that make up 32 working register
organized as Four bank of eight bit each.
 Bits RS0 and RS1 in the PSW determine which bank of register is currently
Is use.
 Bank 0 is selected upon reset

2.Bit addressable:
 A bit addressable area of 16 bytes occupies RAM bytes addresses 20h to
2Fh,forming a total of 128 addressable bits.
 An addressable bit may be specified by its bit address of 00h to 7Fh.

3.General purpose:
 A general-purpose RAM area above the bit area,form 30h to 7Fh,addresable
as bytes.
Internal RAM Organization

Sachin Bhalavat (9409049436)


The stack and The
stack pointer (SP)
 The stack is a section of internal RAM used in conjunction with
certain opcodes to store and retrieve data quickly.
 This information could be data or an address
The register used to access the stack is called the SP (stack
pointer) register.
SP holds internal RAM address that is called the top of the
stack. The stack pointer in the 8051 is only 8 bit wide.
The stack is normally high in internal RAM, by an appropriate
choice of number placed in SP register, to avoid conflict with the
register, bit, and scratch pad internal RAMs.
Stack operation

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