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Lab Micro-Processor, Micro-Controller and Interfacing:: Basic Part 1

The document summarizes the internal architecture of the 8086 microprocessor. It describes the execution unit which contains an ALU and eight registers for storing data. It also describes the bus interface unit which facilitates communication between the EU and memory or I/O modules. Finally, it discusses the various CPU registers including general purpose registers, segment registers, pointer/index registers, and the flags register which determines the status of arithmetic operations.

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65 views15 pages

Lab Micro-Processor, Micro-Controller and Interfacing:: Basic Part 1

The document summarizes the internal architecture of the 8086 microprocessor. It describes the execution unit which contains an ALU and eight registers for storing data. It also describes the bus interface unit which facilitates communication between the EU and memory or I/O modules. Finally, it discusses the various CPU registers including general purpose registers, segment registers, pointer/index registers, and the flags register which determines the status of arithmetic operations.

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রাকিবুল ইসলাম বাবু
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Lab Micro-processor, Micro-controller and

Interfacing:
Basic part 1

Book read
Assembly language programming Ytha Yu
Chapter 3.2 Organization of. The 8086 Microprocessors

Prepared by:
Nasif M. (Lecturer, Dept. of CSE, UIU.)

Department of Computer Science & Engineering (CSE), United International University (UIU).
8086 Micro-processor (Internal architecture)

Department of Computer Science & Engineering (CSE), United International University (UIU).
Execution Unit (EU)

The purpose of the execution unit (EU) is to execute


instructions. It contains a module called the arithmetic
and logic unit (ALU). The ALU can perform arithmetic (+,
- , x ,%) and logic (AND, OR, NOT} operations. The data for
the operations are stored in registers. A register is like a
memory location except that we normally refer to it by a
name rather than a number. The EU has eight registers for
storing data; their names arc AX, BX, CX, DX, SJ, DI, BP,
and SP. In addition, the EU contains temporary registers
for holding operands for the ALU, and the FLAGS register
whose individual bits reflect the result of a computation.

Department of Computer Science & Engineering (CSE), United International University (UIU).
Bus Interface Unit (BIU)

The bus interface unit (BIU) facilitates communication


between the EU and the memory or I/o modules. It is
responsible for transmit addresses, data, and control signals
on the buses. Its registers are named CS, DS
ES, SS and IP. They hold addresses of memory locations.

The EU and BIU works together. While the EU is executing an


instruction, the BIU fetches up to six byte of the next
instruction and places them in the instruction queue. This
operation is called instruction prefetch. The purpose is to
speed up the process. If the EU needs to communicate with
memory or the peripherals, the BIU suspends instruction
prefetch and performs the needed operations.

Department of Computer Science & Engineering (CSE), United International University (UIU).
CPU Registers
• General purpose registers
• Segment registers
• Pointer and Index Registers
• Flags register

Department of Computer Science & Engineering (CSE), United International University (UIU).
General Purpose Registers

 AX (accumulator register):
 Stores operands for arithmetic & data transfer instructions.

 BX Register (base register):


 Holds the starting base address of a memory within a data segment.

CX Register (counter register):
 Primarily used in loop instruction to store loop counter.

DX Register (data register)
 Used to contain I/O port address for I/O instruction.

6
General Purpose Registers (contd.)

 Each of these 16-bit registers are further subdivided into two 8-bit
registers.

AX AH AL
BX BH BL
CX CH CL
DX DH DL

7
Memory Segmentation registers

ES
64 KB

SS
64 KB

CS
64 KB

DS
64 KB

8086 Memory 8
Pointer and Index registers
 IP: Instruction Pointer
 Points to Next Instruction in code Memory.
 SP: Stack pointer
 Pointer to the top of the stack.
 BP: Base Pointer
- Used to point to the base of the stack.
 SI & DI: Source and Destination Index
register
 is required for string operation
Flag Register

 Flag register determines the current status of the microprocessor.


 It is modified automatically by CPU after mathematical operations.
 This allows to determine the type of the result.

 8086 has 16-bit Flag register.


 There are two kinds of flags: Status Flags and Control Flags

10
Flag Register (contd.)

Status Flags Control Flags


Carry Flag (CF) Trap Flag
Auxiliary-carry Flag (AF) Interrupt Flag
Zero Flag (ZF) Directional Flag
Sign Flag (SF)
Parity Flag (PF)
Overflow Flag (OF)

11
Flag Register (contd.)

Flag Purpose
Carry (CF) CF = 1 if there is a carry out from the MSB on addition or
there is a Borrow into the MSB on subtraction.
Parity (PF) PF=1 if the low byte of a result has an even number of one bits
(even parity).
Auxiliary (AF) Holds the carry (half–carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic instruction
execution. SF=1 if the MSB of a result is 1.

12
Flag Register (contd.)

Flag Purpose
Trap (TF) Enables the trapping through an on-chip debugging feature.

Controls the operation of the INTR (interrupt request)


Interrupt (IF) IF = 0 if the INTR pin is disabled
IF = 1, if the INTR pin isenabled.

Selects either the increment or decrement mode for DI


Direction (DF) and /or SI registers during the string instructions.

Overflow occurs when signed numbers are added or


Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the machine.

13
Segmentation and offset
 Book chapter: 3.2.3 Segment Registers

14
Segmentation and offset
 Book chapter: Ytha yu 3.2.3 Segment Registers
 Memory Segment

A memory segment is a block of 64 KB memory blocks. Each segment


is identified by a segment number, starting with 0000H. A segment
number is 16 bits, so the highest segment number is FFFFH.
Within a segment, a memory location is specified by an offset. This is
the number of bytes from the beginning of the segment. The first
byte in a segment has offset 0. The last offset in a segment is FFFFH.

 Segment: Offset Address

A memory location may be specified by providing a segment number


and an offset, written in the form segment:offset; this is known as a
logical address. For example, A4FB:4872h means offset 4872H within
segment A4FBH. 15

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