02 CH4 Part 01 RT and Microoperation
02 CH4 Part 01 RT and Microoperation
• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers
• Register Transfer
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
MICROOPERATIONS (1)
MICROOPERATION (2)
R f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
Computer Organization Computer Architecture
Register Transfer & -operations 8 Register Transfer Language
- Microoperations set
DESIGNATION OF REGISTERS
MAR
– Registers may also be represented showing the bits of data they contain
DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
REGISTER TRANSFER
– In this case the contents of register R2 are copied (loaded) into register R1
– A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2
REGISTER TRANSFER
– the data lines from the source register (R5) to the destination register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action
CONTROL FUNCTIONS
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called
a control function
– If the signal is 1, the action takes place
P: R2 R1
Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1) then (R2 R1)
t t+1
Timing diagram
Clock
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS
P: R3 R5, MAR IR
• Here, if the control function P = 1, load the contents
of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR
CONNECTING REGISTRS
Bus lines
B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder
S0 0
Select 1
S1 2
Enable 3
MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits
containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the
following
– n data input lines
data input lines
– n data output lines
– k address lines n
– A Read control line
address lines
– A Write control line
k
RAM
Read
unit
Write
n
data output lines
MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as
a device, M.
• Since it contains multiple locations, we must specify
which address in memory we will be using
• This is done by indexing memory references
M
Memory Read
AR
unit Write
MEMORY READ
MEMORY WRITE
M[MAR] R1
• This causes the following to occur
– The contents of the MAR get sent to the memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus to the data input lines
of the memory
– The values get loaded into the specified address in the memory
Solve the following problems from the CH4 of the text book “Computer
System Architecture” 3rd Edition, by M. Morris Mano
4-1, 4-3, 4-6, 4-7