CSE 3205: Microprocessor and

Assembly Language
Marjia Sultana
Lecturer
Department of Computer Science and Engineering
Begum Rokeya University, Rangpur
Lecture 4: Pin Diagram of 8086
Pin Diagram of 8086
 Intel 8086-Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

4
Pin Functions
• Out of 40 pins, 32 pins are having same function in minimum or
maximum mode,
• And remaining 8 pins are having different functions in minimum and
maximum mode.
• Following are the pins which are having same functions
 Common Pin Description

VCC – Pin number 40 – At this pin, the external power

supply of + 5V is provided to the processor.

VSS – Pin number 1 and 20 – These two pins acts as the

ground. This pin directs the extra current of the
microprocessor to ground.
 Common Pin Description

AD0 – AD15 – Pin number 2 to 16 and 39 – These are the

multiplexed address and data bus.
We know that the 8086 microprocessor has 20-bit address
bus and 16-bit data bus. So, the 16 lines of the address and
data bus are multiplexed together so as to reduce the
number of lines inside the IC.
 Common Pin Description

A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20

address bits, 4 are present in the multiplexed form with the status
signals. In the case of memory operations, these pins act as an address
bus and contain the memory address of any particular instruction or
data.
However, from I/O operations these pins are low that shows the status
of the processor.
Basically, the signal at S3 and S4 show that which segment is currently
accessed by the microprocessor among the four segments present in it.
The table below will show the encoding of S3 and S4:
 Common Pin Description

Also, S5, when enabled, shows the presence of an

interrupts in the microprocessor. So, basically, it serves as
an interrupt flag.
The signal at S6 shows the status of the bus master for the
current operation. More simply we can say, whether the
8086 is the bus master or any other proficient device is
acting as the bus master.
When 0 is present as the signal at this pin then it indicates
the 8086 is holding the access of the bus otherwise it is
high i.e., 1.
 Common Pin Description

BHE’ / S7 – Pin number 34 – BHE is an acronym for Bus High Enable. The
combination of the BHE signal and S7 status informs about the existence of
the data on the bus. Also, different combinations show whether the bus is
containing overall 16 bit, upper byte or lower byte of the data.
The table below represents the status for the signal at this pin:
 Common Pin Description

MN/MX’ – Pin number 33 –The status at this particular pin

shows whether the processor is operating in the minimum
mode or maximum mode.
A signal 0 at this pin informs that the 8086 is operating in
maximum mode i.e., multiple processors. While signal 1
shows the operation under minimum mode i.e., single
processor.
 Commmon Pin Description

RD’ – Pin number 32 – An active low signal at this pin

shows that the microprocessor is performing read
operation with either memory or I/O devices.
CLK – Pin number 19 –  A signal at this pin provides the
timing to the internal operations that are being executed
inside the microprocessor.
 Common Pin Description

NMI – Pin number 17 – NMI is Non-maskable interrupt.

These are basically uncontrollable interrupts generated
inside the processor. When an NMI occurs, then an
interrupt service routine is generated by the interrupt
vector table.
TEST – Pin number 23 – This pin basically shows the wait
instruction. Whenever a low signal at this pin occurs then
the processing inside the processor continues. As against,
in case of the high signal, the processor has to wait for the
disabling of this pin.
 Common Pin Description

INTR – Pin number 18 – INTR stands for an interrupt

request. The processor after each clock cycle samples the
INTR and if the signal at this pin is found to be high then
the processor controls that interrupt internally.
READY – Pin number 22 – This signal is used by the
peripherals and memory devices in order to show the
readiness for the next operation.
RESET – Pin number 21 – Whenever this pin is enabled
then it resets the processor and other devices connected to
the system by immediately terminating the recent task.
 Pins in Minimum Mode

INTA’ – Pin number 24 – It is an interrupt acknowledge pin.

Whenever an INTR signal is generated, then the
microprocessor generates INTA signal, as a response to that
interrupt.
ALE –Pin number 25 -Address Latch Enable:
When high, multiplexed address/data bus contains address
information
.
 Pins in Minimum Mode

DEN’ – Pin number 26 – DEN is used for data enable. This is

an active low pin that means whenever a 0 is present at
this pin then the transceiver gets enabled and it separates
the data from the multiplexed address and data bus.
DT/R’ – Pin number 27 – This pin is used to show whether
the data is getting transmitted or is received. A high signal
at this pin indicates that data is being transmitted. While a
low indicates reception of data.
.
.
 Pins in Minimum Mode

M/IO’ – Pin number 28 – This pin indicates whether the processor is

performing an operation with memory or I/O devices. Whenever a high is
present at this pin then it shows the operation is carried out through the
memory. While a low signal shows operation through I/O devices.
WR’ – Pin number 29 – An active low signal at this pin indicates that the
processor is performing write operation from either memory or I/O
devices.
HOLD – Pin number 31 – When an external device enables this pin then
the processor stops accessing the buses immediately after the recent task
gets over.
HLDA – Pin number 30 – This pin is used as a response pin for the hold
request. Once request for accessing the buses is produced by an external
entity. Then the microprocessor acknowledges the device that its request
will be considered once it gets over by the current operation..
.
 Pins in Maximum Mode

S0‘, S1‘ and S2‘ – Pin number 26 to 28 – These are basically 3 status pins
and are active low. This means that if the status at all the 3 pins is 0
then it shows that multiple interrupts are to be handled in maximum
mode.
The table below is representing the status of the processor in different
combinations:
S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state
 Pins in Maximum Mode

QS0 and QS1 – Pin number 24 and 25 – These two pins

indicate the status of the 6-byte pre-fetch queue present in
the architecture of 8086.
 Pins in Maximum Mode

LOCK’ – Pin number 29 –This pin is involved in maximum

mode operation. So, basically, when a single processor is
accessing the buses and peripherals then it locks the
resources being used by it. So, that no other entity can
access it until the recent processor frees it.
RQ’/ GT0‘ and RQ’/ GT1‘ –  Pin number 30 and 31 – Due to
the involvement of multiple processors, these pins indicate
the request and grant permission for accessing the buses,
memory and peripherals.
Lecture 5: Addressing Modes of 8086
Addressing Mode
• The addressing mode is the method to specify the operand of an
instruction. The job of a microprocessor is to execute a set of
instructions stored in memory to perform a specific task. Operations
require the following:
• The operator or opcode
• The operands
• An assembly language program instruction consists of two parts
Example: ADD 7,8
Opcode Operand
Addressing Mode
• IMPORTANT TERMS
• Starting address of memory segment.
• Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and
index.
• Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
• Base: Contents of base register, BX or BP.
• Index: Content of index register SI or DI.
 Types of 8086 Addressing Mode
The 8086 has 8 basic addressing modes:
1) Immediate addressing mode
2) Register addressing mode
3) Direct memory addressing mode
4) Register based indirect addressing mode
5) Register relative addressing mode
6) Indexed addressing mode
7) Base indexed addressing mode
8) Relative based indexed addressing mode
9) Implied addressing mode
Types of Addressing Mode
1) Immediate addressing mode-
• In this mode, the operand is specified in the instruction itself.
Instructions are longer but the operands are easily identified.
• Example:
• MVI CL, 12H
• This instruction moves 12 immediately into CL register. CL ← 12H
 Types of Addressing Mode
2) Register addressing mode-
• In this mode, operands are specified using registers. This addressing
mode is normally preferred because the instructions are compact and
fastest executing of all instruction forms.
• Registers may be used as source operands, destination operands or both.
• Example:
• MOV AX, BX
• This instruction copies the contents of BX register into AX register.
AX ← BX
Types of Addressing Mode
3) Direct memory addressing mode
• In this mode, address of the operand is directly specified in the
instruction. Here only the offset address is specified, the segment being
indicated by the instruction.
• Example:
• MOV CL, [4321H]
• This instruction moves data from location 4321H in the data segment
into CL.
• The physical address is calculated as
• DS * 10H + 4321
• Assume DS = 5000H
• ∴PA = 50000 + 4321 = 54321H
• ∴CL ← [54321H]
Types of Addressing Mode
4) Register based indirect addressing mode
• In this mode, the effective address of the memory may be taken directly
from one of the base register or index register specified by instruction. If
register is SI, DI and BX then DS is by default segment register.
• If BP is used, then SS is by default segment register.
• Example:
• MOV CX, [BX]
• This instruction moves a word from the address pointed by BX and BX + 1
in data segment into CL and CH respectively.
• CL ← DS: [BX] and CH ← DS: [BX + 1]
• Physical address can be calculated as DS * 10H + BX.
Types of Addressing Mode
5) Register relative (Based) addressing mode-
• In this mode, the operand address is calculated using one of the base
registers and an 8 bit or a 16 bit displacement.
• Example:
• MOV CL, [BX + 04H]
• This instruction moves a byte from the address pointed by BX + 4 in data
segment to CL.
• CL ← DS: [BX + 04H]
• Physical address can be calculated as DS * 10H + BX + 4H.
Types of Addressing Mode
6) Indexed addressing mode-
In this addressing mode, the operands offset address is found by adding the
contents of SI or DI register and 8-bit/16-bit displacements.
Example

MOV BX, [SI+16], ADD AL, [DI+16]

Types of Addressing Mode
7) Base indexed addressing mode-
• Here, operand address is calculated as base register plus an index
register.
• Example:
• MOV CL, [BX + SI]
• This instruction moves a byte from the address pointed by BX + SI in
data segment to CL.
• CL ← DS: [BX + SI]
• Physical address can be calculated as DS * 10H + BX + SI.
Types of Addressing Mode
8) Relative based indexed addressing mode
• In this mode, the address of the operand is calculated as the sum of base
register, index register and 8 bit or 16 bit displacement.
• Example:
• MOV CL, [BX + DI + 20]
• This instruction moves a byte from the address pointed by BX + DI + 20H
in data segment to CL.
• CL ← DS: [BX + DI + 20H]
• Physical address can be calculated as DS * 10H + BX + DI + 20H.
Types of Addressing Mode
9) Implied addressing mode
• In this mode, the operands are implied and are hence not specified in
the instruction.
• Example:
• STC
• This sets the carry flag.
Other Addressing Mode
String Addressing Mode
Employed in string operations to operate on string data.

• The effective address (EA) of source data is stored in SI register and the EA of destination is stored in DI register.

• Segment register for calculating base address of

• source data is DS and that of the destination data is ES

•Example: MOVS BYTE

• Operations:

• Calculation of source memory location:

• EA = (SI) BA = (DS) x 1610 MA = BA + EA

• Calculation of destination memory location:

• EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE

• (MAE)  (MA)

• If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1

• If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
Other Addressing Mode
Addressing Modes for Accessing I/O Ports
Standard I/O uses port addressing modes. Two types:
i) I/O mode (direct):
 
Port number is an 8 bit immediate operand. Example: OUT 05 H, AL
Outputs [AL] to 8 bit port 05 H
 
ii) I/O mode (indirect):
 
The port number is taken from DX.
Example 1: IN AL, DX
 If [DX] = 5040
 8 bit content by port 5040 is moved into AL.
Example 2: IN AX, DX
 Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
Offset for the Specific Segment

Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Address in the stack
ES BX, DI, SI Address of destination data
(for string operations)
Lecture 6: Instruction Set of 8086
Microprocessor
Instruction Set of 8086
The 8086 microprocessor supports 8 types of instructions
1) Data Transfer Instructions
2) Arithmetic Instructions
3) Bit Manipulation Instructions
4) String Instructions
5) Program Execution Transfer Instructions (Branch & Loop Instructions)
6) Processor Control Instructions
7) Iteration Control Instructions
8) Interrupt Instructions
Data Transfer Instruction

1) Data Transfer Instructions

These instructions are used to transfer the data from the source
operand to the destination operand. Following are the list of
instructions under this group −
Data Transfer Instruction
Instruction to transfer a word
• MOV − Used to copy the byte or word from the provided source to
the provided destination.
• PUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided
location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.
- Is equivalent to MOV AL, [AL] [BX]
Data Transfer Instruction
Instructions for input and output port transfer
• IN − Used to read a byte or word from the provided port to the accumulator.
Fixed port addressing: IN AX, 38H
OUT 38H, AL
Variable port Addressing: IN AL, DX; IN AX, DX; OUT DX, AL; OUT DX, AX
• OUT − Used to send out a byte or word from the accumulator to the provided
port.
• Instructions to transfer the address
• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.
Data Transfer Instruction
Instructions to transfer flag registers
• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag
register.
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE
MOV D, S D=S MOV AX, [SI]
PUSH D pushes D to the stack PUSH DX
POP D pops the stack to D POP AS
XCHG D, S exchanges contents of D XCHG [2050], AX
and S
IN D, S copies a byte or word IN AX, 38H
from S to D IN AX, DX
OUT D, S copies a byte or word OUT 05, AL
from D to S
Data Transfer Instruction

OPCODE OPERAND EXPLANATION EXAMPLE

LEA D, S Load effective LEA AX, [BX]
address
LDS D, S Load register and DS LDS BX, [CX]
LES D, S Load register and ES LES BX, [CX]
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

translates a byte in AL XLAT

XLAT none using a table in the equivalent to MOV AL,
memory [AL] [BX]

loads AH with the lower

LAHF none byte of the flag register LAHF
AHFlag register(0-7)
stores AH register to
lower byte of the flag
SAHF none register SAHF
AHFlag register(0-7)

copies the flag register at

the top of the stack
PUSHF none PUSHF
FlagStack
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

copies a word at the top

of the stack to the flag
register POPF
POPF none
StackFlag
Arithmetic Instruction
Arithmetic Instructions These instructions are used to perform
arithmetic operations like addition, subtraction, multiplication, division,
etc.
Arithmetic Instruction
Following is the list of instructions under this group
• Instructions to perform addition
• ADD − Used to add the provided byte to byte/word to word. ADC −
Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction
operation.
Arithmetic Instruction
• Instructions to perform subtraction
• SUB − Used to subtract the byte from byte/word from word.
• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• NPG − Used to negate each bit of the provided byte/word and add
1/2’s complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.
Arithmetic Instruction
• *Instruction to perform multiplication
• MUL − Used to multiply unsigned byte by byte/word by word.
• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.
Arithmetic Instruction
• *Instructions to perform division
• DIV − Used to divide the unsigned word by byte or unsigned double
word by word.
• IDIV − Used to divide the signed word by byte or signed double word
by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign
bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign
bit of the lower word.
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

ADD D, S D=D+S ADD AX, [2050]

ADC D, S D = D + S + prev. carry ADC AX, BX

SUB D, S D=D–S SUB AX, [SI]

SBB D, S D = D – S – prev. carry SBB [2050], 0050

MUL 8-bit register AX = AL * 8-bit reg. MUL BH

MUL 16-bit register DX AX = AX * 16-bit MUL CX

reg.

IMUL 8 or 16 bit register performs signed IMUL CX

multiplication
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE
DIV 8-bit register AX = AX / 8-bit reg. ; AL = DIV BL
quotient ; AH = remainder

DIV 16-bit register DX AX / 16-bit reg. ; AX = DIV CX

quotient ; DX = remainder
IDIV 8 or 16 bit register performs signed division IDIV BL
INC AX
INC D D=D+1 INC [BX] memory
INC[1000] ] direct memory

DEC AL
DEC D D=D–1 DEC [CX] memory
DEC [1000] direct memory
CBW none converts signed byte to CBW
word
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

CWD none converts signed byte to CWD

double word

NEG D D = 2’s compliment of D NEG AL

CMP AX, CX
CMP Mem/Reg1, Mem/Reg1-Mem/Reg1
Mem/Reg1 Subtract two values AX-CXflag [modify]
Never store subtract
result
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

DAA none decimal adjust DAA

accumulator

ASCII adjust
AAA none accumulator after AAA
addition
ASCII adjust
AAS none accumulator after AAS
subtraction
ASCII adjust
AAM none accumulator after AAM
multiplication
ASCII adjust
AAD none accumulator after AAD
division
Logical Instruction
OPCODE OPERAND DESTINATION EXAMPLE

AND D, S D = D AND S AND AX, 0010

OR D, S D = D OR S OR AX, BX

NOT D D = NOT of D NOT AL

XOR D, S D = D XOR S XOR AL, BL

performs bit-wise AND

TEST D, S operation and affects TEST [0250],
the flag register
Logical Instruction
OPCODE OPERAND DESTINATION EXAMPLE
shifts each bit in D to
SHR D, C the right C times and 0 SHR AL, 04
is stored at MSB
position
shifts each bit in D to
SHL D, C the left C times and 0 is SHL AX, BL
stored at LSB position
ROR D, C rotates all bits in D to ROR BL, CL
the right C times
ROL R, C rotates all bits in D to ROL BX, 06
the left C times
rotates all bits in D to
RCR D, C the right along with RCR BL, CL
carry flag C times
rotates all bits in D to
RCL R, C the left along with RCL BX, 06
carry flag C times
Unconditional Program Execution Transfer Instruction

Opcode Operand Description

CALL address Used to call a procedure and save

their return address to the stack.

RET ---- Used to return from the

procedure to the main program.

Used to jump to the provided

JMP address address to proceed to the next
instruction.

Used to loop a group of

LOOP address instructions until the condition
satisfies, i.e., CX = 0
Conditional Program Execution Transfer Instruction
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential
order.
Following is the list of instructions under this group −
•REP − Used to repeat the given instruction till CX ≠ 0
Eg. REP MOVSB STR1 STR2
It copies byte to byte contents
REP repeats the operation MOVSB until CX becomes zero
•MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
•COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
•INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided
memory location.
•OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
•SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or
string word with a word in AX.
Processor Control Instruction
OPCODE OPERAND EXPLPANATION EXAMPLE
STC none sets carry flag to 1 STC
CLC none resets carry flag to 0 CLC
CMC none compliments the carry CMC
flag
sets directional flag to
STD none 1 STD
resets directional flag
CLD none to 0 CLD

STI none sets the interrupt flag STI

to 1
CLI none resets the interrupt flag CLI
to 0
 Example:
• Determine the effect of each one of the following 8086 instructions:
• i) PUSH [BX]
• ii) DIV DH
• iii) CWD
• iv) MOVSB
• v) MOV START [BX], AL
Assume the following data prior to execution of each one of the above instructions
independently.
[DS]=3000H, [ES]=5000H, [DX]=0400H, [SP]=5000H, [SS]=6000H, [AX]=00A9H, [SI]=0400H,
DF=0, [BX]=6000H, Value of START=05H
[36000H]=02H, [36001]=03H
[50500H]=05H
[30400H]=02H, [30401H]=03H