Logic Circuits

Fundamentals of Instrumentation and Control

PD2 – ES4
(Lecture – VIII)
 Logic Circuits
• Flip Flops
– One bit storage
• Registers
– Multi bit storage
• Counters
– Counting and timing
• Adders
– Addition and subtraction
 Flip Flops
• A sequential electronic circuit which has two stable states
• Capable of serving as one bit of memory, either 1 or 0
• If we give some input in Flip-Flop and then we remove the input,
the output will be same and it will show the previous Output state
• Four main types
– RS (Reset/Set) or SC (Set/Clear) Flip Flop
• Asynchronous
• Synchronous
– JK- Flip Flop
– D (Data) Flip Flop
– T (Toggle) Flip Flop
 Flip Flops
• If Q = 0 ,it will said to be RESET, Low state, Logic 0 or clear
• If Q = 1 , it will said to be SET, High state or Logic 1
• We can change the Output States By changing the Inputs,
• This is why this system is called FLIP-FLOP
• Also called Latch as it latches the input till it is forced to clear
 SR Latch or Basic Flip Flop
• We can design Latches by using both NAND or
NOR Gate
• Also called SC (Set/Clear) Flip Flop
 NAND Based RS Flip Flop
•• Working state of input is 0 which is R S Q Q’ State
 
memorized 0 0 1 1 Racing
– A zero at is memorized as Q=1
– A zero at is memorized as Q=0
0 1 0 1 Reset
1 0 1 0 Set
• Case 1 : S = 1 , R = 0 we will get Q = 0 ,
Q’ = 1 No Change
1 1 Q Q’
(Memory)
• Case 2 : S = 0 , R = 1 we will get Q = 1 ,
Q’ = 0
• Case 3: If we remove the input, then,
S = 1 , R = 1 we will get same output,
showing the memory characteristics
• Case 4 : S = 0 , R = 0 we will get Q = 1 ,
Q’ = 1 which is of no use and is called
racing condition
 NOR Based RS Flip Flop
•• Working state of input is 1 which is R S Q Q’ State
 
memorized No Change
0 0 Q Q’
– A one at is memorized as Q=1 (Memory)
– A one at is memorized as Q=0 0 1 1 0 Set
• Case 1 : S = 1 , R = 0 we will get Q = 1 , 1 0 0 1 Reset
Q’ = 0
1 1 0 0 Racing
• Case 2 : S = 0 , R = 1 we will get Q = 0 ,
Q’ = 1
• Case 3: If we remove the input, then,
S = 0 , R = 0 we will get same output,
showing the memory characteristics
• Case 4 : S = 1 , R = 1 we will get Q = 0 ,
Q’ = 0 1 which is of no use and is
called racing condition
 Synchronization
• Used when changes are to be limited at certain time defined by a
synchronization signal called clock. The synchronization signal is
called clock because it decides the time of input
• We can change the circuit speed by changing the Clock frequency

• Synchronization can be performed when the clock is

– level high (high level triggered synchronization)
– level low (low level triggered synchronization)
– going low to high (leading/rising/positive edge triggered synchronization)
– going high to low (trailing/falling/negative edge triggered synchronization)
– or any other combination

• Edge triggered synchronization is most widely used in digital

systems
 Synchronization

Clock Signal Clocked RS Flip Flop

Clocked RS Flip Flop (NAND)

S* = S’ + CK ‘ R* = R’ + CK’
 Clocked RS Flip Flop (NAND)
• Case 1 : S = 0 and R = 0 then S* = 1 and R* = 1
• Case 2 : S = 0 and R = 1 then S* = 1 and R* = 0
• Case 3 : S = 1 and R = 0 then S* = 1 and R* = 0
• Case 4 : S = 1 and R = 1 then S* = 0 and R* = 0
CLK S R Qn Q’ n Qn+1
0 X X Memory Qn
1 0 0 No Change
1 0 1 0 1 0
1 1 0 1 0 1
1 1 1 1 1 Racing
 D (Data) Flip Flop
• In the clocked SR flip flop
– The input is memorized until the next clock signal is provided
– S input is always opposite to R input for useful conditions
• This can be used to store the bit value and provide the clock only when a
change is desired
• We don’t need two separate inputs but one and its compliment
connected to the second input

RS
 JK Flip Flop
Qn Q’ n Qn+1
• TO USE THE NOT USED CLK J K
0 X X Memory
CONDITION OF S-R Qn
1 0 0 No Change
FLIPFLOP WE NEED TO 1 0 1 0 1 0
1 1 0 1 0 1
USE THE J-K FLIP FLOP
Q n’
1 1 1 X X
Toggle
• When Clock occurs and
J and K both are in set
condition the output
will invert from present
state i.e. Toggle
 T Flip Flop
• Simply obtained by tying both the J and K inputs of a JK Flip
Flop together
• Very useful for counting applications and frequency division
applications

CLK T Qn+1

0 to1 0 Qn

Qn
0 to 1 1

1 to 0 0 Qn

Q’n
1 to 0 1
(Toggle)
 Binary Counters
• Constructed from T (or JK) flip-flops
by taking the output of one cell to
the clock input of the next and tying
the inputs (T or J and K) of each flip-
flop to 1 to produce a toggle at each
cycle of the clock input
• For each two toggles of the first cell,
a toggle is produced in the second,
and so on down to the fourth cell
• Taking the levels of all outputs gives a
binary number equal to the number
of cycles of the input clock signal as
X 3 X 2 X1 X 0
 Down Counters
• The counters may count the number of pulses both upwards and downwards
• The counter we studied earlier is an up counter as it counts from all zeroes to all
ones
• The counter that counts from all ones to all zeroes is called a down counter
• A down counter may simply be designed using the complementary output Q’ of
the flip flops for the outputs rather than Q
 Up/Down Counters
• Also called Bidirectional Counters
• The circuit is designed to have an additional input to choose between up
and down counting
 Registers
• Made using multiple D flip flops operating
with single clock
 Shift Registers
• Take input serially through one data line only
• Used to convert serial data into parallel
 Digital Adders
• Digital Logic Circuits that can be used to add bits together
• Have two output bits
1. Sum
2. Carry
• There are two basic circuits
1. Half Adder: Adds 2 bits
2. Full Adder: Adds 3 bits.
• Byte addition is performed using full adders in parallel with carry out of
each bit as third input (called “Carry in”) to full adder circuit of higher bit
• Subtraction can be performed by adding negative (2’s complement) of
the byte to be subtracted
 Half Adder
Bit 1 Bit 2 Sum Sum Carry
(A) (B) Bit (S) Bit (C)
0 0 00 0 0
0 1 01 1 0
1 0 01 1 0
1 1 10 0 1

 •Sum =
• Carry =
 Full Adder
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

• Sum=Cin⊕(A⊕B)
• Cout=(A.B)+(Cin.(A⊕B)
 4 Bit Binary Adders
• One half adder and any
number of full adder cells can
be connected together to
form an n-bit addition
• In this design, there is no Cin
input
• Inputs A and B are four bits
wide, and bit 0 (A(0) and B(0))
are the LSBs
• Sum is also four bit wide with
a Carry-Out as fifth bit
 Binary Adder/ Subtractor
• Subtraction is addition of negative
• Negative are represented as 2’s complement
• 2’s complements are obtained by adding a 1 to
LSB of 1’s complement
• An additional signal (K) may decide whether
the number is to be subtracted (1) or added
(0)
Binary Adder/ Subtractor
 XOR Gate as Controlled Inverter
Control Bit Data Bit Output
K B Q
Q= • XOR Gate can be used as
0 0 0 controlled inverter
B
0 1 1
1 0 1
• When the control input K is
B´ 0, it transfers the controlled
1 1 0
input B as it is to the output
• When the control input K is
1, it transfers the
complement B’ of the
controlled input B to the
output