Scribd
Upload
226 views36 pages

UNIT-1: TOPIC: MOS Process, NMOS Process, CMOS Process

1. The document describes the process of fabricating a CMOS chip, which uses both NMOS and PMOS transistors. 2. Key steps include growing an oxide layer, depositing photoresist and using masks to define regions, doping wells through diffusion or implantation, depositing polysilicon for gates, and doping source and drain regions. 3. The process concludes with depositing aluminum for interconnections, removing excess metal, and forming terminals to complete the CMOS chip.

Uploaded by

ashish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
226 views36 pages

UNIT-1: TOPIC: MOS Process, NMOS Process, CMOS Process

1. The document describes the process of fabricating a CMOS chip, which uses both NMOS and PMOS transistors. 2. Key steps include growing an oxide layer, depositing photoresist and using masks to define regions, doping wells through diffusion or implantation, depositing polysilicon for gates, and doping source and drain regions. 3. The process concludes with depositing aluminum for interconnections, removing excess metal, and forming terminals to complete the CMOS chip.

Uploaded by

ashish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 36

UNIT-1

TOPIC : MOS Process,


NMOS Process, CMOS
Process
N-MOS Fabrication Process
1. Processing is done on thin wafer cut from a single crystal of
Si of high priority

Si-substrate

Fig. (1) Pure Si single crystal

 Required P-impurities are added as crystal is ground

------------------------
-------------------------
--------------------------
-------------------------
Fig. (2) P-type impurity is lightly
doped
2. A thick layer of SiO2 (thick OX) is thermally ground on wafer.

 Insulated substrate on to which others layer may be deposited


and patterned

Thick SiO2
(1 µm)
-----------------------
- - - - - - - - - - - - - - - - - - -P - - - - -
--------------------------
--------------------------
3. The surface is now covered with a photoresist which
is deposited onto the wafer and to achieve an even
distribution of the required thickness.

Fig. (3) SiO2 Deposited over si surface


4. A mask is placed on PR layer. Which defines there
regions into diffusion is to take place together with
transmission channels.
Uv light passed---area exposed to light hardened.
The unaffected area is etched away with underlying thick OX.
 The remaining PR is removed.
5. Thin oxide layer is grown and then polysilicon is
deposited on by chemical vapors deposition (CVD)
techniques.
6) The gate is formed by ‘photolithography’
7. The n-type impurities are diffused in the exposed p-substrate
from source and drain.
• *Diffusion is done by heating the wafer to a high temperature
& passing gas containing the desired n-type impurities over
the surface.

GAT
E
8. Thick OX layer is grown & then by
photolithography ‘contact cuts’ are formed.
9. Then metal is (Al) deposited over chip & by
photolithography the required interconnection pattern is
formed.
CMOS PROCESS
What is CMOS?

CMOS technology uses both nMOS and pMOS transistors. The


transistors are arranged in a structure formed by two
complementary networks
 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel

 It facilitates low- power dissipation and high-packing density


with very less noise margin. It is mostly used to build digital
circuitry
Fabrication Process-Basic steps
 Fabrication process, circuit design process and performance of the
resulting chip strongly depend on each other
 Circuit designer should have a clear understanding of various masks
 Masks – Each processing step requires certain areas
to be defined on the chip by masks
 Lithography – The process used to transfer a pattern
to a layer on the chip
 Wells – To accommodate both nmos & pmos
devices, special regions called wells or tubs are
created.
Detailed Mask Views
Six masks
– n-well
n well

– Polysilicon
Polysilicon

n+ Diffusion

– N+ diffusion
– P+ diffusion
p+ Diffusion

– Contact Contact

– Metal Metal
CMOS Fabrication Process
CMOS fabrication can be accomplished using
either of the three technologies
 N-well process for CMOS fabrication
 P-well process
 Twin tub-CMOS-fabrication process
Making of CMOS using N well

 Step 1: First we choose a substrate as a base


for fabrication. For N- well, a P-type silicon
substrate is selected.

Substrate
Step2: Oxidation
 The oxidation process is done by using high-purity
oxygen and hydrogen, which are exposed in an
oxidation furnace approximately at 1000 degree
centigrade.

Oxidation
Step3: Photoresist

A light-sensitive polymer that softens whenever exposed


to light is called as Photoresist layer. It is formed.

Growing of Photoresist
Step4: Masking

The photoresist is exposed to UV rays through the N-well mask.

Masking of Photoresist
Step 5: Photoresist removal
 A part of the photoresist layer is removed by treating
the wafer with the basic or acidic solution.
Step 6 – Etching
• The SiO2 oxidation layer is removed through the
open area made by  the removal of photoresist using
hydrofluoric acid.

Etching of SiO2
Step7: Removal of photoresist

• The entire photoresist layer is stripped off, as shown


in the below figure.
Step8: Formation of the N-well

• By using ion implantation or diffusion process N-well


is formed.
Step9: Removal of SiO2

• Using the hydrofluoric acid, the remaining SiO2 is


removed.
Step10: Deposition of Polysilicon

• Chemical Vapor Deposition (CVD) process is used to

deposit a very thin layer of gate oxide.


Step11: Formation of Gate Region
 Removing  the  layer barring a small area for the
Gates
 Except the two small regions required for forming the
Gates of NMOS and PMOS,  the remaining layer is
stripped off
Step12: Oxidation process

 An oxidation layer is formed on this layer with two


small regions for the formation of the gate terminals
of NMOS and PMOS.
Step 13 – Masking and Diffusion
 By using the masking process small gaps are made for the
purpose of N-diffusion.

 The n-type (n+) dopants are diffused or ion implanted, and the
three n+ are formed for the formation of the terminals of
NMOS.
Step 14 – Removal of Oxide: 

• The oxide layer is stripped off.


Step15: P-diffusion
• Similar to the above N-diffusion process, the P-
diffusion regions are diffused to form the terminals of
the PMOS.
Step16: Thick field oxide
• A thick-field oxide is formed in all regions except the
terminals of the PMOS and NMOS.
Step17: Metallization
• Aluminum is sputtered on the whole wafer.
Step18: Removal of excess metal

• The excess metal is removed from the wafer layer.


Step 19 – Formation of Terminals:

•  In the gaps formed after removal of excess metal


terminals are formed for the interconnections.
Step 20 – Assigning the Terminal Names: 

• Names are assigned to the terminals of NMOS and PMOS


transistors.

You might also like