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Advanced Microprocessors: Presented by Ashish Kumar Singh Pranav Gautam Guide Mrs. Nayanica Srivastava

The document provides information about advanced microprocessors such as the 80386 and Pentium. It discusses the architecture and features of these 32-bit processors including their modes of operation, memory management, registers, caches, and superscalar design which allows executing multiple instructions per clock cycle to improve performance. Key aspects covered are the 80386's 32-bit architecture, 4GB physical address space, virtual memory support, and three operation modes. The Pentium introduced superscalar design, branch prediction, separate caches, and higher clock frequencies.

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106 views

Advanced Microprocessors: Presented by Ashish Kumar Singh Pranav Gautam Guide Mrs. Nayanica Srivastava

The document provides information about advanced microprocessors such as the 80386 and Pentium. It discusses the architecture and features of these 32-bit processors including their modes of operation, memory management, registers, caches, and superscalar design which allows executing multiple instructions per clock cycle to improve performance. Key aspects covered are the 80386's 32-bit architecture, 4GB physical address space, virtual memory support, and three operation modes. The Pentium introduced superscalar design, branch prediction, separate caches, and higher clock frequencies.

Uploaded by

Pranav Gautam
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Advanced

Microprocessors

GUIDE PRESENTED BY
Mrs. Nayanica Ashish Kumar Singh
Srivastava Pranav Gautam
INTRODUCTION TO 80386
This 80386 is a 32bit processor that supports, 8bit/32bit data
operands.
The 80386 instruction set is compatible with all its
predecessors.
The 80386 can run 8086 applications under protected mode
in its virtual 8086 mode of operation.
With the 32 bit address bus, the 80386 can address upto
4Gbytes of physical memory. The physical memory is
organised in terms of segments of 4Gbytes at maximum.
The 80386 CPU supports 16K number of segments and thus
the total virtual space of 4Gbytes * 16K = 64 Terrabytes.
 The memory management section of 80386 supports the
virtual memory, paging and four levels of protection,
maintaining full compatibility with 80286.
The 80386 offers a set of 8 debug registers DR0-DR7 for
hardware debugging and control. The 80386 has on-chip
address translation cache.
The concept of paging is introduced in 80386 that enables
it to organise the available physical memory in terms of
pages of size 4Kbytes each, under the segmented memory.
The 80386 can be supported by 80387 for mathematical
data processing.
Architecture of 80386
The Internal Architecture of 80386 is divided into 3
sections.
Central processing unit
Memory management unit
Bus interface unit
Central processing unit is further divided into Execution
unit and Instruction unit
Execution unit has 8 General purpose and 8 Special
purpose registers which are either used for handling
data or calculating offset addresses.
Pin Diagram of 80386
Modes of Operation
The 80386 has three modes of operation:
Real Address Mode (Real Mode)
Protected Virtual Addressing mode (Protected Mode)
Virtual 8086 mode
Protected mode
Protected mode is the natural 32-bit environment of
the 80386 processor. In this mode all instructions and
features are available.
Real Mode

Real-address mode (often called just "real mode") is


the mode of the processor immediately after RESET. In
real mode the 80386 appears to programmers as a fast
8086 with some new instructions. Most applications of
the 80386 will use real mode for initialization only.
Virtual Mode

Virtual 8086 mode (also called V86 mode) is a


dynamic mode in the sense that the processor can
switch repeatedly and rapidly between V86 mode and
protected mode. The CPU enters V86 mode from
protected mode to execute an 8086 program, then
leaves V86 mode and enters protected mode to
continue executing a native 80386 program.
Introduction To Pentium
Introduced in 1993 with clock frequency ranging
from 60 to 66 MHz
 The primary changes in Pentium Processor were:
– Superscalar Architecture
– Dynamic Branch Prediction
– Pipelined Floating-Point Unit
– Separate 8K Code and Data Caches
– Writeback MESI Protocol in the Data Cache
– 64-Bit Data Bus
– Bus Cycle Pipelining
Pentium Architecture
Pentium Architecture
• It has data bus of 64 bit and address bus of 32-
bit
• There are two separate 8kB caches – one for
code and one for data.
 Prefetch Buffers:
Four prefetch buffers within the processor works as two
independent pairs.
 When instructions are prefetched from cache, they are placed into
one set of prefetch buffers.
The other set is used as when a branch operation is predicted.
 Prefetch buffer sends a pair of instructions to instruction decoder
Instruction Decode Unit:
 It occurs in two stages – Decode1 (D1) and Decode2(D2)
D1 checks whether instructions can be paired
 D2 calculates the address of memory resident operands
Control Unit :
▫ This unit interprets the instruction word and microcode entry point fed to
it by Instruction Decode Unit
▫ It handles exceptions, breakpoints and interrupts.
▫ It controls the integer pipelines and floating point sequences
Microcode ROM :
▫ Stores microcode sequences
 Arithmetic/Logic Units (ALUs) :
▫ There are two parallel integer instruction pipelines: u_x0002_pipeline and
v-pipeline
▫ The u-pipeline has a barrel shifter
▫ The two ALUs perform the arithmetic and logical operations specified by
their instructions in their respective pipeline.
Pentium Registers
 Four 32-bit registers can be used as
∗ Four 32-bit register (EAX, EBX, ECX, EDX)
∗ Four 16-bit register (AX, BX, CX, DX)
∗ Eight 8-bit register (AH, AL, BH, BL, CH, CL, DH,
DL)
 Some registers have special use
∗ ECX for count in loop instructions
Superscalar Processor
A superscalar processor is a CPU that implements a form
of parallelism called instruction-level parallelism within a
single processor.
In contrast to a scalar processor that can execute at most
one single instruction per clock cycle, a superscalar
processor can execute more than one instruction during a
clock cycle by simultaneously dispatching multiple
instructions to different execution units on the processor.
It therefore allows for more throughput (the number of
instructions that can be executed in a unit of time) than
would otherwise be possible at a given clock rate.
Superscalar CPU design emphasizes improving the
instruction dispatcher accuracy, and allowing it to
keep the multiple execution units in use at all times.
This has become increasingly important as the
number of units has increased.
While early superscalar CPUs would have two ALUs
and a single FPU, a later design such as the PowerPC
970 includes four ALUs, two FPUs, and two SIMD
units.

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