Kuliah Rangkaian Digital
Kuliah 5: Desain Rangkaian
Kombinasional
Teknik Komputer
Universitas Gunadarma
1
Topik 5 – Desain Rangkaian
Kombinasional
Task:
Given a description of problem (logical statement), find the
corresponding digital circuits that produce the output (answer)
given a set of inputs (condition).
Contoh-2:
Parking lot controller
Elevator controller
Prime number indicator
Adder, subtractor, …
Brute-force approach
Row N3 N2 N1 N0 F
0 0 0 0 0 0
Design: given a description or truth 1 0 0 0 1 1
table, find the corresponding 2 0 0 1 0 1
Boolean expression and digital 3 0 0 1 1 1
circuit. 4 0 1 0 0 0
5 0 1 0 1 1
Brute-force design methodology: 6 0 1 1 0 0
Truth table canonical sum 7 0 1 1 1 1
SoP or sum of minterms 8 1 0 0 0 0
AND-OR / NAND-NAND 9 1 0 0 1 0
10 1 0 1 0 0
Example: prime number detector 11 0 0 1 1 1
F = (1,2,3,5,7,11,13) 12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
Minterm list -> canonical sum
Algebraic simplification
Recall (T8) X · Y + X · Y’ = X
Simplify equation to reduce number of gates & gate inputs
Resulting circuit
Combinational circuit
design/minimization
Objective:
Minimizing # logic gates
Minimizing # inputs to the logic gates
Note different logic gates may have different # transistors
General idea: simplify the Boolean expression using the
theorems, especially (T10, T10’, T13, T13’)
Karnaugh-map (K-map)
Graphical representation of the truth table
Offers visualization of (T10, T10’)
Works for functions with less than 6 variables
Real world: use programs to minimize logic circuits
E.g., VHDL, Verilog, ABEL, …
Karnaugh-map usage
Plot 1s corresponding to minterms of function.
Circle largest possible rectangular sets of 1s.
# of 1s in set must be power of 2
OK to cross edges
Read off product terms, one per circled set.
Variable is 1 include variable
Variable is 0 include complement of variable
Variable is both 0 and 1 variable not included
Circled sets and corresponding product terms are called
`prime implicants’
Minimum number of gates and gate inputs
3 variable example: F = (1,2,5,7)
Rules of thumb:
Group (prime implicant) as
large (many 1s) as possible
As few groups as possible
Overlaps are OK
4 variable K-map example
Note how it maps to the
rows of the truth table
Prime-number detector revisited
Compare with the previous circuit
When we solved algebraically, we missed one
simplification- the circuit below has three less gate
inputs.
Design example: alarm controller
Problem statement:
The ALARM output is 1 if PANIC is 1, or if ENABLE is 1 and the
house is not secure.
The house is secure if WINDOW, DOOR, GARAGE are all 1
This can be put in logic expressions as follows:
ALARM = PANIC + ENABLE · SECURE’
SECURE = WINDOW · DOOR · GARAGE
ALARM = PANIC + ENABLE · (WINDOW · DOOR · GARAGE)’
Multiply out and use (T13), we get the SoP form
ALARM = PANIC + ENABLE · WINDOW’
+ ENABLE · DOOR’+ ENABLE · GARAGE’
K-map with don’t-cares
In some cases, the output of a combinational circuit
doesn’t matter for certain input combinations.
Such combinations are called don’t-cares and the output
is represented in the truth table and K-maps as `d’.
When using K-maps to minimize such functions:
Allow d’s to be included when grouping sets of 1’s to make the
sets as large as possible.
Do not circle any set that only contains d’s.
Example with don’t-cares
Prime number detection for BCD numbers (takes value between 0-9) –
minterms 10-15 are treated as don’t-cares:
F(N3,N2,N1,N0) = N3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15)
From K-map: N3
N3’· N0
N3 N2
Prime Implicants: 00 01 11 10 N2 · N0
N1 N0
N3’· N0 N2’· N1 N2 · N0 0 4 12 8
00 d
Distinguished 1-cells:
1 5 13 9
Cell 1 covered by N3’· N0 01 1 1 d
Cell 2 covered by N2’· N1 N0
3 7 15 11
11 1 1 d d
Here not all prime implicants are
essential prime implicants that N1
2 6 14 10
must be included minimum 10 1 d d
SOP expression:
F = N3’ · N0 + N2’ · N1
N2 N2’· N1
5-variable K-maps
The K-map for a 5-variable logic function is organized
as two 4-variable K-maps:
Can be visualised as being one 4-variable map on top of
another 4-variable map
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 00
1 5 13 9 17 21 29 25
01 01
Z Z
3 7 15 11 19 23 31 27
11 11
Y Y
2 6 14 10 18 22 30 26
10 10
X X
V=0 V=1
5-variable K-map example
F(V,W,X,Y,Z)
= V,W,X,Y,Z(4,5,6,7,9,11,13,15,25,27,29,31)
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 1 00
1 5 13 9 17 21 29 25
01 1 1 1 01 1 1
Z Z
3 7 15 11 19 23 31 27
11 1 1 1 11 1 1
Y Y
2 6 14 10 18 22 30 26
10 1 10
X X
V=0 V=1
5-variable K-map example – cont.
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 1 00
1 5 13 9 17 21 29 25
01 1 1 1 01 1 1
Z Z
3 7 15 11 19 23 31 27
11 1 1 1 11 1 1
Y Y
2 6 14 10 18 22 30 26
10 1 10
X X
V’ · W’· X V=0 W·Z V=1
Minimum SOP: F = V’ · W’· X + W · Z
K-map product-of-sum minimization
Using K-map, find a minimal PoS expression for
F(X,Y,Z) = X,Y,Z (0,3,4,7)
Truth Table X
XY
Row X Y Z F
0 0 0 0 0 Z 00 01 11 10
1 0 0 1 1 0 2 6 4
2 0 1 0 1 0 0 0
3 0 1 1 0 1 3 7 5
4 1 0 0 0 1 0 0 Z
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0 Y
K-map PoS minimization – cont.
X (Y + Z)
XY
Z 00 01 11 10
0 2 6 4
0 0 0
Truth Table
1 3 7 5
Row X Y Z F 1 0 0 Z
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1 Y
3 0 1 1 0 (Y’ + Z’)
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0 Minimum PoS: F = (Y + Z) · (Y’ + Z’)
K-map PoS minimization – another
example
Using K-map, find a minimal POS expression for
F(W,X,Y,Z) = W,X,Y,Z (1,3,8,10,12,13,14,15)
W
WX
YZ 00 01 11 10
0 4 12 8
00 0 0
1 5 13 9
01 0 0
Z
3 7 15 11
11 0 0
Y
2 6 14 10
10 0 0
X
K-map PoS minimization – another
example
W
WX
00 01 11 10
YZ
0 4 12 8 (W’ + Z)
00 0 0
1 5 13 9
(W + X + Z’)
01 0 0
Z
3 7 15 11
11 0 0
Y
2 6 14 10
10 0 0
(W’ + X’)
X
Minimum POS: F = (W + X + Z’) · (W’ + Z) · (W’ + X’)
Combinational Circuit:
Transient vs. Steady-state Output
Timing Diagram propagation delay
1
X Time
0
X X’
1 0 1
X’
0
Transient Steady-state output
output
Transient output: the temporary output due to the gate propagation
delay(s)
Gate propagation delay: the time it takes to pull up (or down) the
output signals due to the change at the input – depends on the
transistor level implementation.
Hazards in combinational circuits
Output glitch: a momentary (transient) fluctuation in output signal due to
changes in input signal.
1 1 1 1 1
0 0 0 0 0
Static-0 Hazard Static-1 Hazard Dynamic Hazard Example
Static hazards:
Static-0 hazard: The output should be 0 but goes momentary to 1 as a result
of an input change – possible in AND-OR circuits
Static-1 hazard: The output should be 1 but goes momentary to 0 as a result
of an input change – possible in OR-AND circuits
Dynamic hazards: The output changes more than once as a result of a
single input change (impossible in 2-level circuits).
Example: static-1 hazard
A static-1 hazard exists in the following AND-OR circuit when X=1, Y=1
and Z changes from 1 to 0 (assume all gates have propagation delay
Extra propagation delay
Circuit between Z and Z’
1 Timing Diagram
X X · Z’
Z’ 1 0 1
Z 0 1 1
1 0 Z
0
F
1
1 0 Z’
0
1
Y Y·Z 1
Y·Z
0
K-map X
XY 1
Z 00 01 11 10 X·Z’ 0
0 2 6 4 X · Z’ Steady-state
0 1 1
output
1 3 7 5 1
1 Z F
1 1 0
Time
Y Y·Z
Eliminate static-1 hazard using K-map
Static-1 hazards are found using k-maps by finding adjacent 1 cells
that are covered by different product terms.
To eliminate static-1 hazards, additional product terms (prime
implicants) are needed to cover such cells thus covering the transition
of the variable causing the hazard.
For the previous example the static-1 hazard is eliminated by
including the additional product term X · Y
New F = X · Z’ + Y · Z + X · Y
X
X·Y X X · Z’
Z 00 01 11 10 Z’
Z
0 2 6 4 X·Z’
0 1 1 X·Y F
1 3 7 5
1 1 1 Z
Y Y·Z
Y·Z Y X·Y
Eliminate static-0 hazard using K-map
A static-0 hazard occurs in OR-AND circuits when an input
variable and its complement are connected to two different OR
gates.
The procedure to find and eliminate static-0 hazards using K-
maps is done in a dual way to finding static-1 hazards.
Static-0 hazards are found using k-maps by finding adjacent 0
cells that are covered by different sum terms.
To eliminate static-0 hazards, additional sum terms (prime
implicates) are needed to cover such cells thus covering the
transition of the variable causing the hazard.
Homework #2
Turn in: (show your steps)
4.13 (f), 4.14 (f)
4.19 (e), 4.20 (e), 4.21 (e)
4.22 (d)
4.45
4.47 (refer to 4.46 for hints)
4.55 (a) (b) (c)
4.65
4.72 (f), 4.73 (f)
Self exercise: (you do not need to turn in these, but think
about them!!)
4.48, 4.50, 4.52, 4.68, 4.71, 4.84, 4.85
