SUBTHRESHOLD DOMINO

LOGIC GATE

Manoj kumar Sharma

 Dynamic Logic Circuits *
 Dynamic logic is temporary (transient) in that output levels will remain valid only
for a certain period of time
– Static logic retains its output level as long as power is applied
 Dynamic logic is normally done with charging and selectively discharging

 capacitance (i.e. capacitive circuit nodes)

– Precharge clock to charge the capacitance
– Evaluate clock to discharge the capacitance depending on condition of logic inputs
 Advantages over static logic:
– Avoids duplicating logic twice as both N-tree and P-tree, as in standard CMOS
– Typically can be used in very high performance applications
– Very simple sequential memory circuits; amenable to synchronous logic
– High density achievable
– Consumes less power (in some cases)
 Disadvantages compared to static logic:
– Problems with clock synchronization and timing
– Design is more difficult
NMOS Dynamic Logic Basic Circuit
 The basic dynamic logic gate concept is shown at left (top)
– the pass transistor MP is an NMOS device, but could also be
implemented with a transmission gate TG
– Cx represents the equivalent capacitance of the input gate of the
second NMOS device (part of an inverter or logic gate) as well as the
PN junction capacitance of MP’s drain (source)
– When clock CK goes high, MP is turned on and allows the input
voltage Vin to be placed on capacitor Cx
 Vin could be a high (“1”) or a low (“0”) voltage
– When CK goes low, MP is turned off, trapping the charge on Cx
 Operation for a 1 or a 0:
– If Vin is high (say VOH), then MP will allow current to flow into Cx,
charging it up to Vdd – Vtn (assume CK up level is Vdd)
– If Vin is low (say GND), then MP will allow current to flow out of Cx,
discharging it to GND
 Due to leakage from the drain (source) of MP, Cx can only retain
the charge Q for a given period of time (called soft node)
– If MP is NMOS, Cx will discharge to GND
– If MP is PMOS, Cx will discharge to VDD
– If MP is a TG, Cx could discharge in either direction
Dynamic NMOS Logic: Transfer “1” Event
 Charging event with NMOS operating in source-follower
mode:
– MP will be saturated during transfer “1” transient
– Max voltage attainable at Vx will be Vdd – Vtn, assuming that
the CK pulse height is Vdd
– Solve for increasing voltage Vx versus time:
Cx (dVx/dt) = ½ n(Vdd – Vx – Vtn)2
– Solution:
t = (2Cx/ n)[{1/(Vdd – Vx – Vtn) – 1/(Vdd – Vtn)}]
or, solving for Vx(t)
Vx(t) = (Vdd – Vtn)[1 – 1/{1 + (Vdd – Vtn)(n/2Cx)t}]

 As t  infinity, Vx(t)  Vdd – Vtn

 Solve for time needed to reach 90% (Vdd – Vtn):
– Set Vx(t) = 0.9 (Vdd – Vtn)  t90% = 18 Cx/ n(Vdd – Vtn)
 i.e. 18 time constants
Dynamic NMOS Logic: Transfer “0” Event
 On a transfer “0” event, the NMOS transfer device is in its
common source configuration, i.e. the source is at GND and
the drain is discharging Cx
– MP is operating in the linear mode for the entire transient since
the starting value is Vdd – Vtn

– Solve for decreasing Vx with time:

Cx (dVx/dt) = - n Vx (Vdd – Vtn - ½ Vx)2

– Solution:
t = Cx/(n(Vdd – Vtn)) ln{(2(Vdd – Vtn) – Vx)/Vx}

 Solve for time needed for Vx to fall to 10% (Vdd – Vtn):

– Set Vx(t) = 0.1 (Vdd – Vtn)  t10% = 2.9 Cx/ n(Vdd – Vtn)
 i.e. 2.9 time constants
 Therefore, the time to discharge Cx with an NMOS MP pass
transistor is much shorter than the time to charge Cx due to
the source-follower operation during charging.
 Leakage and Subthreshold Current in Dynamic Pass
Gate
 Charge can leak off the storage capacitor Cx mainly from two sources:
– PN junction leakage of the NMOS drain (source) junction
– Subthreshold current (IOFF) through MP when its gate is down at zero volts

 One can solve for the maximum amount of time t that charge can be retained on Cx
using the differential equation C dv/dt = I, where
– I is the total of the reverse PN junction leakage and the I OFF current
– C is the total load capacitance due to gate, junction, wire, and poly capacitance
– the maximum allowable V in order to preserve the logic “1” level is known
 Typically V ~ Vdd – Vtn – ½ Vdd = ½ Vdd – Vtn
 The minimum frequency of operation can be found from f ~ 1/(2 t)
Dynamic Bootstrapping Technique
 Bootstrapping is a technique that is sometimes used to
charge up a transistor gate to a voltage higher than Vdd when
that transistor has to drive a line to the full Vdd
 At left is a NMOS bootstrap driver often used in memory circuits
to drive a highly capacitive word line

 Operation:
– When Vin = high, M1 is on holding Vout low while M3 charges Vx
to Vdd – Vt. Thus, Cboot is charged to Vdd – Vt – VOL
– When Vin goes low, turning M1 off, M2 starts charging Vout high.
If Cboot > Cs, most of the increase in Vout is “booted” to Vx, raising
the voltage at Vx to well above Vdd.

• It is desired to obtain Vx > Vdd + Vt

in order to keep M2 linear, to allow
Vout to be charged fully to Vdd.
• Parasitic capacitor Cs bleeds some of
the charge off Cboot, limiting the max
voltage on Vx (charging coupling eq.)
• At left Cboot is implemented with a
transistor having source tied to drain.
 Dynamic Latches with a Single Clock
 Dynamic latches eliminate dc feedback leg by storing data on gate capacitance of inverter (or
logic gate) and switching charge in or out with a transmission gate
– Minimum frequency of operation is typically of the order of 50-100 KHz so as not to lose data due to
junction or gate leakage from the node
– Can be clocked at high frequency since very little delay in latch elements

 Examples:
– (a) or (b) show simple transmission gate latch concept
– (c ) tri-state inverter dynamic latch holds data on gate when clk is high
– (d) and (e) dynamic D register
Dynamic Registers with Two Phase Clocks
 Dynamic register with pass gates and two
phase clocking is shown
– Clocks phi1 and phi2 are non-overlapping
– When phi1 is high & phi2 is zero,

 1st pass gate is closed and D data charges gate

capacitance C1 of 1st inverter
 2nd pass gate is open trapping prior charge on C2
 When phi1 is low and phi2 is high,
– 1st pass gate opens trapping D data on C1
– 2nd pass gate closes allowing C2 to charge with
inverted D data
 If clock skew or sloppy rise/fall time clock
buffers cause overlap of phi1 and phi2 clocks,
– Both pass gates can be closed at the same time
causing mixing of old and new data and therefore
loss of data integrity!
Two Phase Dynamic Registers (Compact Form)
 Compact implementation of of two phase
dynamic registers shown at left using a tri-
state buffer form.
– Transmission gate and inverter integrated
into one circuit

– Two versions:
 Pass devices closest to output
 Inverter devices closest to output
 Two phase dynamic registers and logic is
often preferred over single phase because
– Due to finite rise and fall times, the CLK and
CLK’ are not truly non-overlapping
– Clock skew often is a problem due to the fact
that CLK’ is usually generated from CLK
using an inverter circuit and also due to the
practical problem of distributing clock lines
without any skew
Dynamic Shift Registers with Enhancement Load
 At left (top) is a dynamic shift register
implemented with a technique named
“ratioed dynamic logic”.
 1 and 2 are non-overlapping clocks
– When 1 is high, Cin1 charges to Vdd – Vt if Vin is
high or to GND if Vin is low

– When 1 drops and 2 comes up, the input

data is trapped on Cin1 and yields a logic
output on Cout1 which is transferred to Cin2
– When 2 drops and 1 comes up again, the
logic output on Cout1 is trapped on Cin2,
which yields a logic output on Cout2, which is
transferred to Cin3, etc.
– To avoid losing too much voltage on the logic
high level, Coutn >> Cinn+1 is desired
– Each inverter must be ratioed to achieve a
desired VOL (e.g. when 2 is high on 1st inv)
 The bottom left dynamic shift register is a
“ratioless dynamic logic” circuit
– When 2 is high transferring data to stage 2,
1 has already turned off the stage 1 load
transistor, allowing a VOL = 0 to be obtained
without a ratio condition between load and
driver transistors.
Dynamic CMOS Logic Gate
 In dynamic CMOS logic a single clock 
can be used to accomplish both the pre-
charge and evaluation operations
– When  is low, PMOS pre-charge transistor

– Mp charges Vout to Vdd, since it remains in

its linear region during final pre-charge

 During this time the logic inputs A1 … B2 are

active; however, since Me is off, no charge
will be lost from Vout
– When  goes high again, Mp is turned off
and the NMOS evaluate transistor Me is
turned on, allowing for Vout to be
selectively discharged to GND depending
on the logic inputs
 If A1 … B2 inputs are such that a conducting
path exists between Vout and Me, then Vout
will discharge to 0
 Otherwise, Vout remains at Vdd
Dynamic CMOS Logic Circuits
 Dynamic CMOS Logic circuits require a
clock to precharge the output node and
then to pull down the logic tree (assuming
the logic inputs provide a path for current to
flow)

– Precharge Phase: clock is down turning on

the P precharge transistor; N pull-down
transistor is off. Output capacitance CN
charges to Vdd.
– Evaluation Phase: clock goes high turning
on the N pull down transistor and turning off
the P precharge transistor. If logic inputs are
such that neg Z is true, then output
capacitance CN discharges to ground.
– No dc current flows during either the
precharge or the evaluate phase.
– Power is dynamic and is given by P
= CN Vdd f  where CN represents an
2

equivalent total capacitance on the output, f

= clock frequency,  =logic repetition rate
 Cascading Problem in Dynamic CMOS Logic
 If several stages of the previous CMOS dynamic logic circuit are cascaded together using
the same clock , a problem in evaluation involving a built-in “race condition” will exist
 Consider the two stage dynamic logic circuit below:
– During pre-charge, both Vout1 and Vout2 are pre-charged to Vdd

– When  goes high to begin evaluate, all inputs at stage 1 require some finite time to resolve, but
during this time charge may erroneously be discharged from Vout2
 e.g. assume that eventually the 1 st stage NMOS logic tree conducts and fully discharges Vout1, but since all
the inputs to the N-tree all not immediately resolved, it takes some time for the N-tree to finally discharge
Vout1 to GND.
 If, during this time delay, the 2 nd stage has the input condition shown with bottom NMOS transistor gate at a
logic 1, then Vout2 will start to fall and discharge its load capacitance until Vout1 finally evaluates and turns
off the top series NMOS transistor in stage 2
– The result is an error in the output of the 2 nd stage Vout2
Cascaded Dynamic CMOS Logic Gates: Evaluate Problem
 With simple cascading of dynamic CMOS
logic stages, a problem arises in the
evaluate cycle:
– The pre-charged high voltage on Node N2
in stage 2 may be inadvertently (partially)

– discharged by logic inputs to stage 2

which have not yet reached final correct
(low) values from the stage 1 evaluation
operation.
– Can not simply cascade dynamic CMOS
logic gates without preventing unwanted
bleeding of charge from pre-charged
nodes
 Possible Solutions:
– two phase clocks
– use of inverters to create Domino Logic
– NP Domino Logic
– Zipper/NORA logic
CMOS Domino Logic
 The problem with faulty discharge of
precharged nodes in CMOS dynamic logic
circuits can be solved by placing an inverter
in series with the output of each gate

– All inputs to N logic blocks (which are derived

from inverted outputs of previous stages)
therefore will be at zero volts during precharge
and will remain at zero until the evaluation
stage has logic inputs to discharge the
precharged node PZ.
– This circuit approach avoids the race problem
of “vanilla” cascaded dynamic CMOS
– However, all circuits only provide non-inverted
outputs
 In (b) a weak P device compensates for
charge loss due to charge sharing and
leakage at low frequency clock operation
 In (c ) the weak P device can be used to latch
the output high
Mixing Domino CMOS Logic with Static CMOS Logic
 We can add an even number of static CMOS inverting logic gates after a Domino logic
stage prior to the next Domino logic stage
– Even number of inverting stages guarantees that inputs to the second Domino logic stage
experience only 0-to-1 transitions (since 1-to-0 transitions may cause an erroneous logic level as
discussed in prior charts 5-67 and 5-68)

 In the cascaded Domino logic structure, the evaluation of each stage ripples through the
cascaded stages similar to a chain of Dominos (from which it takes the name)
– The evaluate cycle must be of sufficient duration to allow all cascaded logic stages (between
latches) to complete their evaluation process within the clock evaluation interval
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